MOSEL VITELIC INC.
Preliminary
MV20556
8 - Bit MCU Mouse Controller
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A full duplex serial I/O port
Working at 16/25/40 MHz Clock
Full static operation: 3 MHz through 16 MHz
July 1997
Features
General 8051 instruction family compatible
Operate at voltage 5.0V.
No External Memory is supported
8 bit bus I/O ports
4 K byte ROM
128 byte RAM
128 byte depth stack
Two 16 bit Timers (Event Counters)
15 programmable I/O pins
Five interrupt sources
Programmable serial UART channel
Direct LED drive output
Description
The MVI MV20556 is an 8 - bit single chip
microcontroller. It provides hardware features and
powerful instruction set that are necessary to make it a
versatile and cost effective controller for mouse
applications which needs up to 4K byte internal
memory either for program or for data and mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications, full
duplex UART.
Pin Configuration
RES
RXD/P 3.0
TXD/P 3.1
XTA2
XTAL1
#INT0/P 3.2
#INT1/P 3.3
T0/P 3.4
1
2
3
4
5
6
7
8
9
10
20
19
VDD
P 1.7
P 1.6
P 1.5
P 1.4
P 1.3
P 1.2
P 1.1
P 1.0
P 3.7
MV20556
20L PDIP
300 mil
(Top View)
20L SOP
(Top View)
18
17
16
15
14
13
12
11
Ordering Information
MV20556ajk - pqrs
a: process identifier. { C:=COMS }
jk: working clock in MHz. { 16 }
pqr: production code { 001, ..., 999 }
s: package type. { P: 20L 300 mil PDIP }
Pin/Pad
Postfix
blank
N
S
Package
dice
20L PDIP
20L SOP
Configuration
page 25
page 1
page 1
Dimension
page 25
page 23
page 24
T1/P 3.5
VSS
Logo Size at
Top Marking
-
4.5 x 3.8 mm
4.0 x 3.4 mm
Specifications subject to change without notice, contact your sales representatives for the most recent information.
1/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
Block Diagram
Decoder &
Register
128 bytes
RAM
4K bytes
ROM
Timer 1
Timer 0
Stack
Pointer
RES
Reset
Circuit
to pertinent blocks
to whole chip
Vdd
Vss
Power
Circuit
Buffer2
Interrupt
Circuit
to pertinent blocks
128
bits
SFR
includes
Acc &
PSW,
etc.
Register
Buffer
Buffer1
DPTR
ALU
PC
Increamenter
XTAL2
XTAL1
Timming
Generator
to whole system
Program
Counter
Port 3
Latch
Port 1
Latch
Port 3
Driver
Port 1
Driver
7
8
Specifications subject to change without notice, contact your sales representatives for the most recent information.
2/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
Pin Descriptions
20L
PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
20L
SOP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
dice
Pad#
4
5
6
7
8
9
10
11
12
13-15
17
18
19
20
21
22
23
24
1
2, 3
Symbol
Active
I/O
Names
RES
RXD/P3.0
TXD/P3.1
XTAL2
XTAL1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
VSS
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VDD
i
i/o
i/o
i
L/-
L/-
o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Reset
bit 0 of Port 3 & Receive data
bit 1 of Port 3 & Transmit data
Crystal out
Crystal in
bit 2 of Port 3 & low true Interrupt 0
bit 3 of Port 3 & low true Interrupt 1
bit 4 of Port 3 & external input to Timer 0
bit 5 of Port 3 & external input to Timer 1
Sink Voltage, Ground
bit 7 of Port 3
bit 0 of Port 1
bit 1 of Port 1
bit 2 of Port 1
bit 3 of Port 1
bit 4 of Port 1
bit 5 of Port 1
bit 6 of Port 1
bit 7 of Port 1
Drive Voltage, +5 Vcc
Signal Descriptions
Vss
Circuit ground potential.
V
DD
+5V power supply during operation.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port.
There is a pull-up resistance when operating at either
input or output.
PORT 3
Port 3 is an 7-bit quasi-bidirectinal I/O port. It also
contains the interrupt and timer as well as serial port
pins that are used by various options. The output latch
corresponding to a secondary function must be
programmed to one (1) for that function to operate.
The secondary functions are assigned to the pins of port
3, as follows:
- RXD/data (P3.0). Serial port's transmitter data input
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.5). Input to counter 1.
There is a pull-up resistance when operating at either
input or output.
RES
A low to high transition on this pin (V IH1) while the
oscillator is not running resets the MV20556. Holding
high signal (higher than V IH1) on this pin for two
machine cycles (24 clocks) or longer while the oscillator
is running, resets the device.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
3/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
Function Overall
The CPU of MV20556 manipulates versatile operands in
four memory spaces. They are 4 KB program ROM,
128-byte internal Data RAM, 20 SFRs and 16-bit program
counter.
The Internal Data Memory address space is further
divided into the 128-byte Internal Data RAM and 128-byte
Special Function Register (SFR) address spaces shown in
latter Figures. Four Register Banks (each with eight
registers), 128 addressable bits, and the stack reside in
the Internal Data RAM. The stack depth is limited only by
the available Internal Data RAM and its location is
determined by the 8-bit Stack Pointer. All registers except
the Program Counter and the four 8-Register Banks reside
in the Special Function Register address space.
These memory mapped registers include arithmetic
registers, pointers, I/O ports, and registers for the interrupt
system, timers and serial channel. 128 bit locations in the
SFR address space are addressable as bits. The
MV20556 contains 128 bytes of Internal Data RAM and 20
SFRs.
The MV20556 provides a non-paged Program Memory
address space to accommodate relocatable code.
Conditional branches are performed relative to the
Program Counter. The register-indirect jump permits
branching relative to a 16-bit base register with an offset
provided by an 8-bit index register. Sixteen-bit jumps and
calls permit branching to any location in the contiguous 4K
Program Memory address space.
The MV20556 has five methods for addressing source
operands: Register, Direct, Register-Indirect, Immediate,
and Base-Register-plus Index-Registe -Indirect
Addressing. The first three methods can be used for
addressing destination operands. Most instructions have
a "destination, source" field that specifies the data type,
addressing methods and operands involved.
For
operations other than moves, the destination operand is
also a source operand.
Any register in the four 8-Register Banks can be accessed
through Register, Direct, or Register-Indirect Addressing;
the 128 bytes of Internal Data RAM through Direct or
Register-Indirect Addressing; and the Special Function
Registers through Direct Addressing. External Data
Memory is accessed through Register-Indirect
Addressing. Look-Up-Tables resident in Program Memory
can be accessed through Base-Register-plus
Index-Register-Indirect Addressing.
The MV20556 is classified as an 8-bit machine since the
internal ROM, RAM, Special Function Registers,
Arithmetic/Logic Unit and external data bus are each 8 bits
Specifications subject to change without notice, contact your sales representatives for the most recent information.
wide. The MV20556 performs operation on bit, nibble,
byte and double-byte data types.
The MV20556 has extensive facilities for byte transfer,
logic, and integer arithmetic operations. It excells at bit
handling since data transfer, logic and conditional branch
operantions can be performed directly on Boolean
variables.
4/27
PID256** 07/97
MOSEL VITELIC INC.
Preliminary
MV20556
Memory Map Overall
The CPU of MV20556 is able to access three memory areas. They are:
(1) 128 bytes data RAM addressed at 00H through 7FH;
(2) 20 SFRs addressed at 80H through FFH;
(3) 4,096 bytes program ROM addressed at 000H through FFFH.
Be noted, MCU MV20556 builds all accessible memory inside, it is unable to access external memory.
4095
FFFH
255
128
127
0
Internal
Data
RAM
FFH
80H
7FH
00H
255
128
FFH
F0H
0
Special
Function
Register
Internal Program ROM
000H
Internal Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
5/27
PID256** 07/97
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