Virtex-7 T and XT FPGAs Data Sheet:
DC and Switching Characteristics
DS183 (v1.10) December 24, 2012
Advance Product Specification
Introduction
Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and
-2L speed grades, with -3 having the highest performance.
The -2L devices operate at V
CCINT
= 1.0V and are screened
for lower maximum static power. The speed specification of
a -2L device is the same as the -2 speed grade. The -2G
speed grade is available in devices utilizing Stacked Silicon
Interconnect (SSI) technology. The -2G speed grade
supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as
well as the standard -2 speed grade specifications.
Virtex-7 T and XT FPGA DC and AC characteristics are
specified in commercial, extended, and industrial
temperature ranges. Except the operating temperature
range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1 speed grade
industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades
and/or devices are available in each temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Virtex-7 T and XT FPGA data sheet, part of an overall
set of documentation on the 7 series FPGAs, is available on
the Xilinx website at
www.xilinx.com/7.
All specifications are subject to change without notice.
DC Characteristics
Table 1:
Absolute Maximum Ratings
(1)
Symbol
FPGA Logic
V
CCINT
V
CCAUX
V
CCBRAM
V
CCO
V
CCAUX_IO
V
REF
V
IN(2)(3)(4)
V
CCBATT
V
MGTAVCC
V
MGTAVTT
V
MGTVCCAUX
V
MGTREFCLK
V
MGTAVTTRCAL
V
IN
Internal supply voltage
Auxiliary supply voltage
Supply voltage for the block RAM memories
Output drivers supply voltage for 3.3V HR I/O banks
Output drivers supply voltage for 1.8V HP I/O banks
Auxiliary supply voltage
Input reference voltage
I/O input voltage
I/O input voltage for V
REF
and differential I/O standards
Key memory battery backup supply
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
1.1
2.0
1.1
3.6
2.0
2.06
2.0
V
CCO
+ 0.5
2.625
2.0
V
V
V
V
V
V
V
V
V
V
Description
Min
Max
Units
GTX and GTH Transceivers
Analog supply voltage for the GTX/GTH transmitter and receiver circuits
Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers
GTX/GTH transceiver reference clock absolute input voltage
Analog supply voltage for the resistor calibration circuit of the GTX/GTH transceiver
column
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
1.1
1.32
1.935
1.32
1.32
1.26
V
V
V
V
V
V
© 2011–2012 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
DS183 (v1.10) December 24, 2012
Advance Product Specification
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1
Virtex-7 T and XT FPGAs Data Sheet: DC and Switching Characteristics
Table 1:
Absolute Maximum Ratings
(1)
(Cont’d)
Symbol
I
DCIN
I
DCOUT
Description
DC input current for receiver input pins DC coupled V
MGTAVTT
= 1.2V
DC output current for transmitter pins DC coupled V
MGTAVTT
= 1.2V
XADC supply relative to GNDADC
XADC reference input relative to GNDADC
Min
–
–
Max
14
14
Units
mA
mA
XADC
V
CCADC
V
REFP
–0.5
–0.5
2.0
2.0
V
V
Temperature
T
STG
T
SOL
T
j
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
The lower absolute voltage specification always applies.
For I/O operation, refer to
UG471:
7 Series FPGAs SelectIO Resources User Guide.
The maximum limit applied to DC and AC signals.
For maximum undershoot and overshoot AC specifications, see
Table 4
and
Table 5.
For soldering guidelines and thermal considerations, see
UG475:
7 Series FPGA Packaging and Pinout Specification.
Storage temperature (ambient)
Maximum soldering temperature for Pb/Sn component bodies
(6)
Maximum soldering temperature for Pb-free component bodies
(6)
Maximum junction temperature
(6)
–65
–
–
–
150
+220
+260
+125
°C
°C
°C
°C
2.
3.
4.
5.
6.
Table 2:
Recommended Operating Conditions
(1)
Symbol
FPGA Logic
Internal supply voltage
V
CCINT(2)
Internal supply voltage for -1C devices with voltage identification (VID) bit
programmed to run at 0.9V typical
(3)
.
Block RAM supply voltage
V
CCBRAM(2)
V
CCAUX
V
CCO(4)(5)
V
CCAUX_IO
V
IN(6)
I
IN(7)
V
CCBATT(8)
Block RAM supply voltage for -1C devices with voltage identification (VID)
bit programmed to run at 0.9V typical
(3)
.
Auxiliary supply voltage
Supply voltage for 3.3V HR I/O banks
Supply voltage for 1.8V HP I/O banks
Auxiliary supply voltage when set to 1.8V
Auxiliary supply voltage when set to 2.0V
I/O input voltage
I/O input voltage for V
REF
and differential I/O standards
Maximum current through any pin in a powered or unpowered bank when
forward biasing the clamp diode.
Battery voltage
0.97
0.87
0.97
0.87
1.71
1.14
1.14
1.71
1.94
–0.20
–0.20
–
1.0
1.00
0.90
1.00
0.90
1.80
–
–
1.80
2.00
–
–
–
–
1.03
0.93
1.03
1.03
1.89
3.465
1.89
1.89
2.06
V
CCO
+ 0.2
2.625
10
1.89
V
V
V
V
V
V
V
V
V
V
V
mA
V
Description
Min
Typ
Max
Units
GTX and GTH Transceivers
Analog supply voltage for the GTX/GTH transceiver QPLL frequency range
≤
10.3125 GHz
(10)(11)
Analog supply voltage for the GTX/GTH transceiver QPLL frequency range
> 10.3125 GHz
0.97
1.02
1.0
1.05
1.08
1.08
V
V
V
MGTAVCC(9)
DS183 (v1.10) December 24, 2012
Advance Product Specification
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2
Virtex-7 T and XT FPGAs Data Sheet: DC and Switching Characteristics
Table 2:
Recommended Operating Conditions
(1)
(Cont’d)
Symbol
V
MGTAVTT(9)
V
MGTVCCAUX(9)
V
MGTAVTTRCAL(9)
Description
Analog supply voltage for the GTX/GTH transmitter and receiver
termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers
Analog supply voltage for the resistor calibration circuit of the GTX/GTH
transceiver column
Min
1.17
1.75
1.17
Typ
1.2
1.80
1.2
Max
1.23
1.85
1.23
Units
V
V
V
XADC
V
CCADC
V
REFP
XADC supply relative to GNDADC
Externally supplied reference voltage
1.71
1.20
1.80
1.25
1.89
1.30
V
V
Temperature
Junction temperature operating range for commercial (C) temperature
devices
T
j
Junction temperature operating range for extended (E) temperature
devices
Junction temperature operating range for industrial (I) temperature devices
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
All voltages are relative to ground.
V
CCINT
and V
CCBRAM
should be connected to the same supply.
For more information on the VID bit see
XAPP555,
Lowering Power using the Voltage Identification Bit.
Configuration data is retained even if V
CCO
drops to 0V.
Includes V
CCO
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
The lower absolute voltage specification always applies
A total of 200 mA per bank should not be exceeded.
V
CCBATT
is required only when using bitstream encryption. If battery is not used, connect V
CCBATT
to either ground or V
CCAUX
.
Each voltage listed requires the filter circuit described in
UG476:
7 Series FPGAs GTX/GTH Transceiver User Guide.
For data rates
≤
10.3125 Gb/s, V
MGTAVCC
should be 1.0V ±3% for lower power consumption.
For lower power consumption, V
MGTAVCC
should be 1.0V ±3% over the entire CPLL frequency range.
0
0
–40
–
–
–
85
100
100
°C
°C
°C
Table 3:
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRI
I
REF
I
L
C
IN(2)
Description
Data retention V
CCINT
voltage (below which configuration data might be lost)
Data retention V
CCAUX
voltage (below which configuration data might be lost)
V
REF
leakage current per pin
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 3.3V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 2.5V
Min
0.75
1.5
–
–
–
90
68
34
23
12
68
45
–
–
Typ
(1)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
–
–
15
15
8
330
250
220
150
120
330
180
25
150
Units
V
V
µA
µA
pF
µA
µA
µA
µA
µA
µA
µA
mA
nA
I
RPU
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.8V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.5V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.2V
Pad pull-down (when selected) @ V
IN
= 3.3V
Pad pull-down (when selected) @ V
IN
= 1.8V
Analog supply current, analog circuits in powered up state
Battery supply current
I
RPD
I
CCADC
I
BATT(3)
DS183 (v1.10) December 24, 2012
Advance Product Specification
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3
Virtex-7 T and XT FPGAs Data Sheet: DC and Switching Characteristics
Table 3:
DC Characteristics Over Recommended Operating Conditions
(Cont’d)
Symbol
Description
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_40) for commercial (C), industrial (I), and extended (E)
temperature devices
R
IN_TERM
(4)
Min
28
Typ
(1)
40
Max
55
Units
Ω
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_50) for commercial (C), industrial (I), and extended (E)
temperature devices
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_60) for commercial (C), industrial (I), and extended (E)
temperature devices
35
50
65
Ω
44
60
83
Ω
n
r
Notes:
1.
2.
3.
4.
Temperature diode ideality factor
Temperature diode series resistance
–
–
1.010
2
–
–
–
Ω
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
Termination resistance to a V
CCO
/2 level.
Table 4:
Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks
(1)
AC Voltage Overshoot
V
CCO
+ 0.40
V
CCO
+ 0.45
V
CCO
+ 0.50
V
CCO
+ 0.55
V
CCO
+ 0.60
V
CCO
+ 0.65
V
CCO
+ 0.70
V
CCO
+ 0.75
V
CCO
+ 0.80
V
CCO
+ 0.85
V
CCO
+ 0.90
V
CCO
+ 0.95
Notes:
1.
A total of 200 mA per bank should not be exceeded.
% of UI @–40°C to 100°C
100
100
100
100
46.6
21.2
9.75
4.55
2.15
1.02
0.49
0.24
AC Voltage Undershoot
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
–0.75
–0.80
–0.85
–0.90
–0.95
% of UI @–40°C to 100°C
100
61.7
25.8
11.0
4.77
2.10
0.94
0.43
0.20
0.09
0.04
0.02
DS183 (v1.10) December 24, 2012
Advance Product Specification
www.xilinx.com
4
Virtex-7 T and XT FPGAs Data Sheet: DC and Switching Characteristics
Table 5:
Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks
(1)(2)
AC Voltage Overshoot
V
CCO
+ 0.40
V
CCO
+ 0.45
V
CCO
+ 0.50
V
CCO
+ 0.55
V
CCO
+ 0.60
V
CCO
+ 0.65
V
CCO
+ 0.70
V
CCO
+ 0.75
V
CCO
+ 0.80
V
CCO
+ 0.85
V
CCO
+ 0.90
V
CCO
+ 0.95
Notes:
1.
2.
A total of 200 mA per bank should not be exceeded.
For UI smaller than 20 µs.
% of UI @–40°C to 100°C
100
100
100
100
50.0
50.0
47.0
21.2
9.71
4.51
2.12
1.01
AC Voltage Undershoot
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
–0.75
–0.80
–0.85
–0.90
–0.95
% of UI @–40°C to 100°C
100
100
100
100
50.0
50.0
50.0
50.0
50.0
28.4
12.7
5.79
Table 6:
Typical Quiescent Supply Current
Symbol
I
CCINTQ
Description
Quiescent V
CCINT
supply current
Device
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
Speed Grade
-3
1483
N/A
1012
1324
1578
2214
2214
N/A
N/A
1
N/A
1
1
1
1
1
N/A
N/A
-2/-2L/-2G
1483
3756
1012
1324
1578
2214
2214
2580
3448
1
1
1
1
1
1
1
1
1
-1
1483
3756
1012
1324
1578
2214
2214
2580
3448
1
1
1
1
1
1
1
1
1
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
CCOQ
Quiescent V
CCO
supply current
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
DS183 (v1.10) December 24, 2012
Advance Product Specification
www.xilinx.com
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