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ORSPI4-3FE1036C2: DescriptionDual SPI4 Interface and High-Speed SERDES FPSC; File Size1MB，263 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ORSPI4-3FE1036C2 Overview

Dual SPI4 Interface and High-Speed SERDES FPSC

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ORCA

ORSPI4

Dual SPI4 Interface

and High-Speed SERDES FPSC

October 2007

Data Sheet

Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on

the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two

SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b

encoding and decoding and over 600K programmable system gates all on a single chip.

Embedded SPI4 Core Features

■

OIF-SPI4-02.0 compliant interfaces

Dynamic timing receive interface:

• Full bandwidth up to 450 MHz DDR (900

Mbits/s) for all speed grades.

• Bit de-skewing up to 16 phases of the clock

• Capable of aligning bit-to-bit skews as large as

±1 bit periods

Static timing receive interface:

• Speeds up to 325 MHz DDR (650 Mbits/s), for

all speed grades, including Quarter-Rate mode

• Clock aligned or clock centered modes sup-

ported

DIP-4 and DIP-2 parity generation and checking

Transmit Interface:

• Speeds up to 450 MHz DDR (900 Mbits/s)

• Dedicated LVDS transmit interface for improved

data eye integrity

• Automatic idle insertion

256 logical ports:

• Embedded Calendar-based sequence port poll-

ing mechanism and bandwidth allocation.

Shadow Calendar support for smooth transition

to new Calendar

• Up to 32 independent TX and 32 independent

RX buffers per SPI4 interface internally. Various

aggregation modes to support 1 to 32 separate

embedded buffers per TX and RX

• Up to 4 independent TX and 4 independent RX

clock domain transfers to the FPGA logic

FIFO status support modes:

• 1/4 rate LVTTL or 1/4 rate LVDS

• Automatic status handling or optionally under

user control. Credit calculations based on burst

size and status are also handled automatically

Conﬁguration options as suggested in the OIF-

SPI4-02.0 standard

• Conﬁgures parameters such as maximum burst

size, calendar length, main and shadow calen-

dars (1K deep each), length of training

sequence etc.

■

Simple FIFO interface to the FPGA logic

• Provides ease of design and efﬁcient clock

domain transfers

Loopback modes provided for system- and

chip-level debug

Embedded 32-bit internal system bus plus 4-bit

parity

• Interconnects FPGA logic, microprocessor inter-

face (MPI), embedded RAM blocks, and embed-

ded core blocks

• Includes built-in system registers that act as the

control and status center for the device

Low power operation.

• Full-rate SPI4.2 interfaces running at 450 MHz

DDR (900 Mbits/sec) with dynamic alignment

consumes 1.5 W of power or less. More efﬁcient

than FPGAs with soft-IP SPI4 solutions which

consume in excess of 10 W.

Programmable Minburst capability with

selectable burst values ranging from 16 to 240.

Interoperability demonstrated with ORSPI4

partners.

Quad 600 Mbits/s to 3.7 Gbits/s SERDES:

• IEEE 802.3ae XAUI (Link State Machine &

Alignment FIFOs embedded)

• ANSI X3.230:1994 1G/2G FC-compliant (Link

State Machine & Alignment FIFOs embedded)

• Proven performance (same SERDES used in

ORT82G5/ORT42G5 FPSCs)

High Performance Memory Controller for

interface to external buffer memory

• Required for Layer 2 data buffering

• QDR II memory interface:

– 36-bit Input and 36-bit Output bus, 18-bit address

– 175 MHz clock rates

– 20+ Gbits/s bandwidth

– Supports 2- or 4-word burst mode

– Simple FIFO interface to FPGA

– Integrated PLL for optimized performance

– Proven performance with multiple memory suppliers

■

Embedded SERDES Core Features

■

Embedded Memory Controller Features

■

Note: The term SPI4 refers to OIF SPI-4.2 throughout this document

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

ORSPI4_06

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

High-Speed ORCA Series 4 FPGA

■

Internal performance of > 250 MHz

Over 16K programmable logic elements

1.5V operation (30% less power than 1.8 V operation)

Comprehensive I/O selections including LVTTL, LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT,

DDR, LVDS, bused-LVDS, and LVPECL

1036-pin ftSBGA package provides enough FPGA user I/Os (498) for 4 full-duplex XGMII interfaces, 4

full-duplex PL-3 interfaces, etc; a 40% smaller 1156-pin fpBGA package is available with 356 FPGA user

I/Os

Introduction

The SPI4 blocks provide dual 10 Gbits/s physical-to-link layer interfaces in conformance to the OIF-SPI4-02.0

speciﬁcation. Each block provides a full-duplex interface with an aggregate bandwidth of 13.6 Gbits/s. This is

achieved by using 16 LVDS pairs each for RX and TX operating at a maximum data rate of 900 Mbits/s with a 450

MHz DDR clock. Both static and dynamic alignment are supported at the receive interface. Dynamic alignment is

used to compensate for bit-to-bit skew at higher data rates, where it becomes difﬁcult to meet tight setup/hold

requirements. DIP-4 and DIP-2 parity generation and checking are supported. Data buffering of 8K bytes for both

transmit and receive is provided by embedded Dual-Port RAM in each SPI4 core. Internal 1K deep main and

shadow calendar supports scheduling of up to 256 ports. The Transmit and Receive Status FIFOs can also store

ﬂow control information for up to 256 ports, the maximum speciﬁed in the SPI4 speciﬁcation.

An independent QDRII Memory Controller block provides data buffering between the FPGA logic and external

memory and supports a throughput of greater than 20 Gbits/s. Data is transferred to and from memory through two

sets of 36-bit unidirectional data lines operating at up to 175 MHz DDR. A set of 72 data signals is available to

transfer data across the core-FPGA interface and allows the system to utilize the bandwidth available with second-

generation Quad Data Rate (QDRII) SRAMs. Of the 72 data signals, 8 signals can be either used for parity or data.

A soft IP version of this core is also available to allow a second data buffer on this device.

The High-Speed SERDES block supports four serial links, each operating at up to 3.7 Gbits/s (2.96 Gbits/s data

rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in RX Clock

and Data Recovery (CDR) and transmitter preemphasis. The SERDES block is identical to that in the ORT82G5

FPSC, supports embedded 8b/10b encoding/decoding and implements link state machines for both 10G Ethernet,

and 1G/2G/10G Fibre Channel. The state machines are IEEE P802.3ae/D4.01 XAUI based and also support FC

(ANSI X3.230:1994) link synchronization.

Table 1. ORCA ORSPI4 — Available FPGA Logic

Device

ORSPI4

PFU Rows

PFU

Columns

Total PFUs

2,024

FPGA Max

User I/O

498/356

LUTs

16,192

EBR

Blocks

EBR Bits

(K)

148

Usable*

Gates (K)

471-899

Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate

ranges are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40%

EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR

usage and 4 PLL's.

The ORSPI4 device is offered in two packages: 1036 ftSBGA and 1156 fpBGA. The 1036 package offers 498 FPGA User I/Os while the 1156

package offers 356 FPGA User I/Os. Additionally, the SERDES option is not available on the 1156 package.

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

ORSPI4 Overview

The ORSPI4 FPSC provides two SPI4.2 interface blocks, a Memory Controller and a 4-channel SERDES block,

combined with FPGA logic. Based on the 1.5 V OR4E06 ORCA FPGA, it has a 46 x 44 array of Programmable

Logic Cells (PLCs). The embedded core is attached to the right side of the device, as shown below, and is inte-

grated directly into the FPGA array. A top level diagram of the basic chip conﬁguration is shown in Figure 1.

Figure 1. ORSPI4 Basic Chip Conﬁguration

Memory

Controller I/O

Serial I/O

SPI4 I/O

Embedded Core

Memory

Controller

FPGA Programmable I/O

SPI4.2

I/F

ORCA 4E06-Based

Programmable Logic

SPI4.2

I/F

Shared I/O

Quad

SERDES

Each of the logic blocks in the embedded core is functionally independent from the other blocks. Connections

between blocks must be made through the FPGA logic. However, one of the SPI4 blocks and the SERDES block

share I/Os. Hence the device may be conﬁgured to provide either two SPI4 interfaces or one SPI4 interface and

one serial interface.

What Is an FPSC?

FPSCs, or Field-Programmable System Chips, are devices that combine ﬁeld-programmable logic with ASIC or

mask-programmed logic on a single device. FPSCs provide the time to market and the ﬂexibility of FPGAs, the

design effort savings of soft Intellectual Property (IP) cores, and the speed, design density, and economy of ASICs.

FPSC Overview

Lattice’s Series 4 FPSCs are created from Series 4

ORCA

FPGAs. To create a Series 4 FPSC, several columns of

Programmable Logic Cells are integrated with an embedded logic core. Other than replacing some FPGA gates

with ASIC gates, at greater than 10:1 area efﬁciency, none of the FPGA functionality is changed—all of the Series

4 FPGA capability is retained including the Embedded Block RAMs, MicroProcessor Interface (MPI), boundary

scan, etc. Pins from the replaced columns of programmable logic are used as I/O pins for the embedded core. The

remainder of the device pins retain their FPGA functionality.

FPSC Gate Counting

The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.

Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count

is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

area efﬁcient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with

a much larger gate count.

FPGA/Embedded Core Interface

The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of

interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this

on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and

accounted for in the

ispLEVER

Development System.

Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master

32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-

tions including the Embedded Block RAMs and the microprocessor interface.

Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking

between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global

set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the

FPGA as a system.

For even greater system ﬂexibility, FPGA conﬁguration RAMs are available for use by the embedded core. This

allows for user-programmable options in the embedded core, in turn allowing for greater ﬂexibility. Multiple embed-

ded core conﬁgurations may be designed into a single device with user-programmable control over which conﬁgu-

rations are implemented, as well as the capability to change core functionality simply by reconﬁguring the device.

FPSC Design Kit

Development is facilitated by an FPSC design kit which, together with

ispLEVER

and third-party synthesis and sim-

ulation engines, provides all software and documentation required to design and verify an FPSC implementation.

Included in the kit are the FPSC conﬁguration manager, and compiled

Verilog

simulation models,

HSPICE

and/or

IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with

the

design envi-

ronment, provides a seamless FPSC design environment. More information can be obtained by visiting the Lattice

website at

http://www.latticesemi.com

SPI4 Protocol Overview

The System Packet Interface Level 4, Phase 2 (SPI4) was deﬁned by the Optical Internetworking Forum (OIF) as

an interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applica-

tions requiring up to 10 Gbit/s aggregate bandwidth. The system level model for the SPI4 interface is shown in Fig-

ure 2.

ORSPI4-3FE1036C2 Related Products

	ORSPI4-3FE1036C2	ORSPI4-1F1156C	ORSPI4-1FE1036C2	ORSPI4-1FN1156C	ORSPI4-1FTE1036I	ORSPI4-2F1156I	ORSPI4-2FE1036C2	ORSPI4-2FN1156I	ORSPI4-2FTE1036I	ORSPI4-3FN1156C
Description	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC	Dual SPI4 Interface and High-Speed SERDES FPSC

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