KM23C4100D(E)T
4M-Bit (512Kx8 /256Kx16) CMOS MASK ROM
FEATURES
•
Switchable organization
524,288 x 8(byte mode)
262,144 x 16(word mode)
•
Fast access time : 80ns(Max.)
•
Supply voltage : single +5V
•
Current consumption
Operating : 50mA(Max.)
Standby : 50µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. KM23C4100D(E)T : 44-TSOP2-400
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23C4100D(E)T is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 524,288 x 8 bit(byte mode) or as
262,144 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor,
and data memory, character generator.
The KM23C4100D(E)T is packaged in a 44-TSOP2.
FUNCTIONAL BLOCK DIAGRAM
A
17
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(262,144x16/
524,288x8)
PRODUCT INFORMATION
Product
KM23C4100DT
KM23C4100DET
Operating
Temp
0°C~70°C
-20°C~85°C
Vcc
Range
5.0V
Speed
(ns)
80
.
.
.
.
.
.
.
.
A
0
A
-1
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
PIN CONFIGURATION
N.C
1
2
3
4
5
6
7
8
9
44 N.C
43 N.C
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
34 A
16
. . .
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
N.C
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
10
A
0
11
Pin Name
A
0
- A
17
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power(+5V)
Ground
No Connection
CE 12
V
SS
13
OE 14
Q
0
Q
1
Q
9
Q
2
Q
10
15
17
18
19
20
Q
8
16
TSOP
33 BHE
32 V
SS
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
Q
3
21
Q
11
22
KM23C4100D(E)T
KM23C4100D(E)T
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Operating Temperature
Symbol
V
IN
T
BIAS
T
STG
T
A
Rating
-0.3 to +7.0
-10 to +85
-55 to +150
0 to +70
-20 to +85
CMOS MASK ROM
Unit
V
°C
°C
°C
°C
Remark
-
-
-
KM23C4100DT
KM23C4100DET
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum ratin conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
)
Item
Supply Voltage
Supply Voltage
Symbol
V
CC
V
SS
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
=-400µA
I
OL
=2.1mA
Test Conditions
CE=OE=V
IL
, all outputs open
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
Min
-
-
-
-
-
2.2
-0.3
2.4
-
Max
50
1
50
10
10
V
CC
+0.3
0.8
-
0.4
Unit
mA
mA
µA
µA
µA
V
V
V
V
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
L
OE
X
H
L
BHE
X
X
H
L
Q
15
/A
-1
X
X
Output
Input
Mode
Standby
Operating
Operating
Operating
Data
High-Z
High-Z
Q
0
~Q
15
: Dout
Q
0
~Q
7
: Dout
Q
8
~Q
14
: Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE
(T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min8M bit
-
-
Max
10
10
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
KM23C4100D(E)T
AC CHARACTERISTICS
(V
CC
=5V
±
10%, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
CMOS MASK ROM
0.6V to 2.4V
10ns
0.8V and 2.0V
1 TTL Gate and C
L
=100pF
READ CYCLE
Item
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address Change
Symbol
t
RC
t
ACE
t
AA
t
OE
t
DF
t
OH
0
KM23C4100D(E)T-8
Min
80
80
80
40
20
0
Max
KM23C4100D(E)T-10
Min
100
100
100
50
20
0
Max
KM23C4100D(E)T-12
Min
120
120
120
60
20
Max
Unit
ns
ns
ns
ns
ns
ns
TIMING DIAGRAM
READ
ADD
A
0
~A
17
A
-1(*1)
t
ACE
CE
t
OE
OE
t
OH
D
OUT
D
0
~D
7
D
8
~D
15(*2)
VALID DATA
VALID DATA
t
AA
ADD1
t
RC
ADD2
t
DF(*3)
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE=V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
KM23C4100D(E)T
PACKAGE DIMENSIONS
44-TSOP2-400
CMOS MASK ROM
(Unit : mm/inch)
0~8°
(
0.25
)
0.010
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±
0.20
0.463±
0.008
10.16
0.400
(
0.50
)
0.020
#1
#22
1.00±
0.10
0.039±
0.004
1.20
MAX.
0.047
+ 0.10
- 0.05
+ 0.004
0.006
- 0.002
0.15
18.81
MAX.
0.741
18.41±
0.10
0.725±
0.004
(
0.805
)
0.032
0.35±
0.10
0.014±
0.004
0.80
0.0315
0.05
MIN.
0.002
0.10
MAX
0.004
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