PAL16R8ANC datasheet, PDF - EEWORLD Datasheet

PAL16R8ANC: DescriptionProgammable Array Logic Series 24 (PAL Series 24); CategoryProgrammable logic devices Programmable logic; File Size449KB，14 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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PAL16R8ANC Overview

Progammable Array Logic Series 24 (PAL Series 24)

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	National Semiconductor（TI ）
package instruction	DIP, DIP20,.3
Reach Compliance Code	unknown
Architecture	PAL-TYPE
maximum clock frequency	25 MHz
JESD-30 code	R-PDIP-T20
JESD-609 code	e0
length	26.075 mm
Dedicated input times	8
Number of I/O lines
Number of entries	8
Output times	8
Number of product terms	64
Number of terminals	20
Maximum operating temperature	75 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 0 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	20 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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