AT25DF321ASHT datasheet, PDF - EEWORLD Datasheet

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AT25DF321ASHT: DescriptionNOR Flash Serial (SPI, Dual SPI) 3.3V 32M-bit 4M x 8 5ns 8-Pin SOIC EIAJ T/R; File Size989KB，51 Pages; ManufacturerAdesto Technologies

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AT25DF321ASHT Overview

NOR Flash Serial (SPI, Dual SPI) 3.3V 32M-bit 4M x 8 5ns 8-Pin SOIC EIAJ T/R

AT25DF321ASHT Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	3A991.b.1.a
Part Status	Active
HTS	8542.32.00.71
Cell Type	NOR
Chip Density (bit)	32M
Architecture	Sectored
Boot Block	No
Block Organization	Symmetrical
Address Bus Width (bit)	1
Sector Size	64Kbyte x 64
Page Size	256byte
Number of Bits/Word (bit)	8
Number of Words	4M
Programmability	Yes
Timing Type	Synchronous
Max. Access Time (ns)	5
Maximum Erase Time (s)	40/Chip
Maximum Programming Time (ms)	0.007(Typ)/Byte
Interface Type	Serial (SPI, Dual SPI)
Maximum Operating Frequency (MHz)	100
Minimum Operating Supply Voltage (V)	2.7
Typical Operating Supply Voltage (V)	3.3
Maximum Operating Supply Voltage (V)	3.6
Programming Voltage (V)	2.7 to 3.6
Operating Current (mA)	20
Program Current (mA)	16
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	85
Supplier Temperature Grade	Industrial
Command Compatible	Yes
ECC Support	No
Support of Page Mode	No
Minimum Endurance (Cycles)	100000
Packaging	Tape and Reel
Pin Count	8
Standard Package Name	SOP
Supplier Package	SOIC EIAJ
Mounting	Surface Mount
Package Height	1.91(Max)
Package Length	5.35(Max)
Package Width	5.4(Max)
PCB changed	8
Lead Shape	Gull-wing

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Features

•

Single 2.7V - 3.6V Supply

•

Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3

– Supports RapidS Operation

– Supports Dual-Input Program and Dual-Output Read

Very High Operating Frequencies

– 100MHz for RapidS

– 85MHz for SPI

– Clock-to-Output (t

) of 5ns Maximum

Flexible, Optimized Erase Architecture for Code + Data Storage Applications

– Uniform 4-Kbyte Block Erase

– Uniform 32-Kbyte Block Erase

– Uniform 64-Kbyte Block Erase

– Full Chip Erase

Individual Sector Protection with Global Protect/Unprotect Feature

– 64 Sectors of 64-Kbytes Each

Hardware Controlled Locking of Protected Sectors via WP Pin

Sector Lockdown

– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only

128-Byte Programmable OTP Security Register

Flexible Programming

– Byte/Page Program (1- to 256-Bytes)

Fast Program and Erase Times

– 1.0ms Typical Page Program (256-Bytes) Time

– 50ms Typical 4-Kbyte Block Erase Time

– 250ms Typical 32-Kbyte Block Erase Time

– 400ms Typical 64-Kbyte Block Erase Time

Program and Erase Suspend/Resume

Automatic Checking and Reporting of Erase/Program Failures

Software Controlled Reset

JEDEC Standard Manufacturer and Device ID Read Methodology

Low Power Dissipation

– 12mA Active Read Current (Typical at 20MHz)

– 5µA Deep Power-Down Current (Typical)

Endurance: 100,000 Program/Erase Cycles

Data Retention: 20 Years

Complies with Full Industrial Temperature Range

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (208-mil wide)

– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)

•

32-Mbit

2.7V Minimum

Serial Peripheral

Interface Serial

Flash Memory

AT25DF321A

•

3686I–DFLASH–02/2019

Description

The AT25DF321A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer

based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution.

The flexible erase architecture of the AT25DF321A, with its erase granularity as small as 4-Kbytes, makes it ideal for data

storage as well, eliminating the need for additional data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT25DF321A have been optimized to meet the needs of today's code

and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used

much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own

protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory

devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage

segments to be added while still maintaining the same overall device density.

The AT25DF321A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program

and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific

sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in

applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage

segments need to be modified without running the risk of errant modifications to the program code segments. In addition to

individual sector protection capabilities, the AT25DF321A incorporates Global Protect and Global Unprotect features that

allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the

manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming.

To take code and data protection to the next level, the AT25DF321A incorporates a sector lockdown mechanism that allows

any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only. This addresses the

need of certain secure applications that require portions of the Flash memory array to be permanently protected against

malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys,

and routines. The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for

purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in 3V systems, the AT25DF321A supports read, program, and erase operations with a supply

voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.

AT25DF321A

3686I–DFLASH–02/2019

AT25DF321A

Pin Descriptions and Pinouts

Asserted

State

Table 2-1.

Pin Descriptions

Symbol

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted, the device will

be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin

will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is

required to end an operation. When ending an internally self-timed operation such as a program or erase

cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always latched in

on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of

SCK.

SERIAL INPUT (SERIAL INPUT/OUTPUT):

The SI pin is used to shift data into the device. The SI

pin is used for all data input including command and address sequences. Data on the SI pin is always

latched in on the rising edge of SCK.

With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow two bits of

data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To maintain consistency

with SPI nomenclature, the SIO pin will be referenced as SI throughout the document with exception to

sections dealing with the Dual-Output Read Array command in which it will be referenced as SIO.

Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).

SERIAL OUTPUT (SERIAL OUTPUT/INPUT):

The SO pin is used to shift data out from the device.

Data on the SO pin is always clocked out on the falling edge of SCK.

With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to allow two

bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK. To maintain

consistency with SPI nomenclature, the SOI pin will be referenced as SO throughout the document with

exception to sections dealing with the Dual-Input Byte/Page Program command in which it will be

referenced as SOI.

The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted).

WRITE PROTECT:

The WP pin controls the hardware locking feature of the device. Please refer to

“Protection Commands and Features” on page 18

for more details on protection features and the WP

pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not

be used. However, it is recommended that the WP pin also be externally connected to V

whenever

possible.

HOLD:

The HOLD pin is used to temporarily pause serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin

will be ignored, and the SO pin will be in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to

start. A Hold condition pauses serial communication only and does not have an effect on internally self-

timed operations such as a program or erase cycle. Please refer to

“Hold” on page 40

for additional

details on the Hold operation.

The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.

However, it is recommended that the HOLD pin also be externally connected to V

whenever possible.

DEVICE POWER SUPPLY:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

GROUND:

The ground reference for the power supply. GND should be connected to the system ground.

Type

Low

Input

SCK

Input

SI (SIO)

Input/Output

SO (SOI)

Output/Input

Low

Input

HOLD

Low

Input

GND

Power

3686I–DFLASH–02/2019

AT25DF321ASHT Related Products

	AT25DF321ASHT	AT25DF321A-SH-B	AT25DF321A-SH
Description	NOR Flash Serial (SPI, Dual SPI) 3.3V 32M-bit 4M x 8 5ns 8-Pin SOIC EIAJ T/R	NOR Flash Serial (SPI, Dual SPI) 3.3V 32M-bit 4M x 8 5ns 8-Pin SOIC EIAJ Bulk	NOR Flash Serial (SPI, Dual SPI) 3.3V 32M-bit 4M x 8 5ns 8-Pin SOIC EIAJ T/R
EU restricts the use of certain hazardous substances	Compliant	Compliant	Compliant
ECCN (US)	3A991.b.1.a	3A991b.1.a.	3A991.b.1.a
Part Status	Active	Active	Active
HTS	8542.32.00.71	8542.32.00.71	8542.32.00.51
Cell Type	NOR	NOR	NOR
Chip Density (bit)	32M	32M	32M
Architecture	Sectored	Sectored	Sectored
Boot Block	No	No	No
Block Organization	Symmetrical	Symmetrical	Symmetrical
Address Bus Width (bit)	1	1	1
Sector Size	64Kbyte x 64	64Kbyte x 64	64Kbyte x 64
Page Size	256byte	256byte	256byte
Number of Bits/Word (bit)	8	8	8
Number of Words	4M	4M	4M
Programmability	Yes	Yes	Yes
Timing Type	Synchronous	Synchronous	Synchronous
Max. Access Time (ns)	5	5	5
Maximum Programming Time (ms)	0.007(Typ)/Byte	0.007(Typ)/Byte	0.007(Typ)/Byte
Interface Type	Serial (SPI, Dual SPI)	Serial (SPI, Dual SPI)	Serial (SPI, Dual SPI)
Maximum Operating Frequency (MHz)	100	100	100
Minimum Operating Supply Voltage (V)	2.7	2.7	2.7
Typical Operating Supply Voltage (V)	3.3	3.3	3.3
Maximum Operating Supply Voltage (V)	3.6	3.6	3.6
Programming Voltage (V)	2.7 to 3.6	2.7 to 3.6	2.7 to 3.6
Operating Current (mA)	20	20	20
Program Current (mA)	16	16	16
Minimum Operating Temperature (°C)	-40	-40	-40
Maximum Operating Temperature (°C)	85	85	85
Supplier Temperature Grade	Industrial	Industrial	Industrial
Command Compatible	Yes	Yes	Yes
ECC Support	No	No	No
Support of Page Mode	No	No	No
Minimum Endurance (Cycles)	100000	100000	100000
Packaging	Tape and Reel	Bulk	Tape and Reel
Pin Count	8	8	8
Standard Package Name	SOP	SOP	SOP
Supplier Package	SOIC EIAJ	SOIC EIAJ	SOIC EIAJ
Mounting	Surface Mount	Surface Mount	Surface Mount
Package Height	1.91(Max)	1.91(Max)	1.91(Max)
Package Length	5.35(Max)	5.35(Max)	5.35(Max)
Package Width	5.4(Max)	5.4(Max)	5.4(Max)
PCB changed	8	8	8
Lead Shape	Gull-wing	Gull-wing	Gull-wing
Maximum Erase Time (S)	-	40/Chip	40/Chip

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