PRELIMINARY
CY15B108QI
CY15V108QI
Excelon™-LP 8-Mbit (1024K × 8)
Serial (SPI) F-RAM
Excelon™-LP 8-Mbit (1024K × 8) Serial (SPI) F-RAM
Features
■
Functional Description
The Excelon-LP CY15X108QI is a low power, 8-Mbit nonvolatile
memory employing an advanced ferroelectric process. A ferro-
electric random access memory or F-RAM is nonvolatile and
performs reads and writes similar to a RAM. It provides reliable
data retention for 151 years while eliminating the complexities,
overhead, and system-level reliability problems caused by serial
flash, EEPROM, and other nonvolatile memories.
Unlike serial flash and EEPROM, the CY15X108QI performs
write operations at bus speed. No write delays are incurred. Data
is written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared to other
nonvolatile memories. The CY15X108QI is capable of
supporting 10
14
read/write cycles, or 100 million times more write
cycles than EEPROM.
These capabilities make the CY15X108QI ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The CY15X108QI provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
CY15X108QI uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
incorporates a read-only Device ID and Unique ID features,
which allow the host to determine the manufacturer, product
density, product revision, and unique ID for each part. The device
also provides a writable, 8-byte serial number registers, which
can be used to identify a specific board or a system.
For a complete list of related resources,
click here.
8-Mbit ferroelectric random access memory (F-RAM) logically
organized as 1024K × 8
14
❐
Virtually unlimited endurance 100 trillion (10 ) read/writes
❐
151-year data retention (See
Data Retention and Endurance
on page 19)
❐
NoDelay™ writes
❐
Advanced high-reliability ferroelectric process
Fast serial peripheral interface (SPI)
❐
Up to 20 MHz frequency
❐
Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
Sophisticated write protection scheme
❐
Hardware protection using the Write Protect (WP) pin
❐
Software protection using Write Disable (WRDI) instruction
❐
Software block protection for 1/4, 1/2, or entire array
Device ID and Serial Number
❐
Manufacturer ID and Product ID
❐
Unique Device ID
❐
Serial Number
Dedicated 256-byte special sector F-RAM
❐
Dedicated special sector write and read
❐
Stored content can survive up to three standard reflow sol-
dering cycles
Low-power consumption
❐
1.3 mA (typ) active current at 20 MHz
❐
3.0 µA (typ) standby current
❐
0.90 µA (typ) Deep Power Down mode current
❐
0.1 µA (typ) Hibernate mode current
❐
1.6 mA (typ) inrush current during power up
Low-voltage operation
❐
CY15V108QI: V
DD
= 1.71 V to 1.89 V
❐
CY15B108QI: V
DD
= 1.8 V to 3.6 V
Commercial and industrial operating temperature
❐
Commercial operating temperature: 0 °C to +70 °C
❐
Industrial operating temperature:
40
°C to +85 °C
8-pin Grid-Array Quad Flat No-Lead (GQFN) package
Restriction of hazardous substances (RoHS) compliant
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Cypress Semiconductor Corporation
Document Number: 002-18148 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 24, 2018
PRELIMINARY
CY15B108QI
CY15V108QI
Logic Block Diagram
WP
256-Byte
Special Sector
F-RAM
CS
SCK
SI
Instruction Decoder
Control Logic
Write Protect
F-RAM Control
1024K x 8
F-RAM Array
Data I/O Register
SO
Nonvolatile
Status Register
Device ID and Serial
Number Registers
Document Number: 002-18148 Rev. *J
Page 2 of 31
PRELIMINARY
Contents
Pinouts .............................................................................. 4
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Memory Architecture ........................................................ 5
SPI Bus .............................................................................. 5
SPI Overview ............................................................... 5
Terms used in SPI Protocol ......................................... 5
SPI Modes ................................................................... 6
Power-Up to First Access ............................................ 6
Functional Description ..................................................... 7
Command Structure .................................................... 7
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
DC Electrical Characteristics ........................................ 17
Data Retention and Endurance ..................................... 19
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Conditions ........................................................ 19
AC Switching Characteristics ....................................... 20
CY15B108QI
CY15V108QI
Power Cycle Timing ....................................................... 22
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Package Diagram ............................................................ 24
Acronyms ........................................................................ 25
Document Conventions ................................................. 25
Units of Measure ....................................................... 25
Errata ............................................................................... 26
Part Numbers Affected .............................................. 26
Qualification Status ................................................... 26
Errata Summary ........................................................ 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 002-18148 Rev. *J
Page 3 of 31
PRELIMINARY
CY15B108QI
CY15V108QI
Pinouts
Figure 1. 8-pin GQFN Pinout
CS
SO
1
8
V
DD
DNU
SCK
SI
2
7
WP
V
SS
3
6
4
5
TOP View
(Not to Scale)
Pin Definitions
Pin Name
CS
I/O Type
Input
Description
Chip Select.
This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally
activates the SCK signal. A falling edge on CS must occur before every opcode.
Serial Clock.
All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge of the serial clock. The clock frequency may be any value
between 0 and 20 MHz and may be interrupted at any time due to its synchronous behavior.
Serial Input.
All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet the power
(I
DD
) specifications.
Serial Output.
This is the data output pin. It is driven during a read and remains tristated at all other
times. Data transitions are driven on the falling edge of the serial clock SCK.
Write Protect.
This Active LOW pin prevents write operation to the Status Register when WPEN
bit in the Status Register is set to ‘1’. This is critical because other write protection features are
controlled through the Status Register. A complete explanation of write protection is provided in
Status Register
and
Write Protection on page 9.
This pin has an internal weak pull-up resistor which
keeps this pin HIGH if left floating (not connected on the board). This pin can also be tied to V
DD
if
not used.
Do not use.
Either leave this pin floating (not connected on the board) or tie to V
DD
.
SCK
Input
SI
[1]
Input
SO
[1]
WP
Output
Input
DNU
V
SS
V
DD
Do Not Use
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
Note
1. SI may be connected to SO for a single pin data interface.
Document Number: 002-18148 Rev. *J
Page 4 of 31
PRELIMINARY
Functional Overview
The CY15X108QI is a serial F-RAM memory. The memory array
is logically organized as 1,048,576 × 8 bits and is accessed using
an industry-standard serial peripheral interface (SPI) bus. The
functional operation of the F-RAM is similar to serial flash and
serial EEPROMs. The major difference between the
CY15X108QI and a serial flash or EEPROM with the same
pinout is the F-RAM’s superior write performance, high
endurance, and low power consumption.
CY15B108QI
CY15V108QI
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated, the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
Terms used in SPI Protocol
The commonly used terms in the SPI protocol are as follows.
SPI Master
The SPI master device controls the operations on the SPI bus.
An SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
of the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the SCK and all the data transmission on SI and
SO lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. An SPI slave never initiates a communication on the SPI
bus and acts only on the instruction from the master.
The CY15X108QI operates as an SPI slave and may share the
SPI bus with other SPI slave devices.
Chip Select (CS)
To select any slave device, the master needs to pull down the
corresponding CS pin. Any instruction can be issued to a slave
device only while the CS pin is LOW. When the device is not
selected, data through the SI pin is ignored and the serial output
pin (SO) remains in a high-impedance state.
Note
A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
The serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The CY15X108QI supports SPI modes 0 and 3 for data
communication. In both of these modes, the inputs are latched
by the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first Most Significant Bit (MSb) of an
SPI instruction on the SI pin. Further, all data inputs and outputs
are synchronized with SCK.
Memory Architecture
When accessing CY15X108QI, the user addresses 1,024K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the SPI
protocol, which includes a chip select (to permit multiple devices
on the bus), an opcode, and a three-byte address. The upper
four bits of the address range are ‘don’t care’ values. The
complete address of 20 bits specifies each byte address
uniquely.
Most functions of the CY15X108QI are either controlled by the
SPI interface or handled by on-board circuitry. The access time
for the memory operation is essentially zero, beyond the time
needed for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike a serial flash or
EEPROM, it is not necessary to poll the device for a ready
condition because writes occur at bus speed. By the time a new
bus transaction can be shifted into the device, a write operation
is complete. This is explained in more detail in the interface
section.
SPI Bus
The CY15X108QI is an SPI slave device and operates at speeds
of up to 20 MHz. This high-speed serial bus provides high-perfor-
mance serial communication to an SPI master. Many common
microcontrollers have hardware SPI ports allowing a direct
interface. It is simple to emulate the port using ordinary port pins
for microcontrollers that do not have this feature. The
CY15X108QI operates in SPI Modes 0 and 3.
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on the SPI bus is activated using the CS
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both of these modes, data is clocked into the F-RAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
Document Number: 002-18148 Rev. *J
Page 5 of 31
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