DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
General Description
The DA14581 integrated circuit is an optimized version
of the DA14580, offering a reduced boot time and sup-
porting up to 8 connections. It has a fully integrated
radio transceiver and baseband processor for
Blue-
tooth
®
low energy.
It can be used as a standalone
application processor or as a data pump in hosted sys-
tems.
The DA14581 supports a flexible memory architecture
for storing Bluetooth profiles and custom application
code, which can be updated over the air (OTA). The
qualified
Bluetooth low energy
protocol stack and the
HCI ready software are stored in a dedicated ROM. All
software runs on the ARM
®
Cortex
®
-M0 processor via
a simple scheduler.
The
Bluetooth low energy
firmware includes the
L2CAP service layer protocols, Security Manager
(SM), Attribute Protocol (ATT), the Generic Attribute
Profile (GATT) and the Generic Access Profile (GAP).
All profiles published by the Bluetooth SIG as well as
custom profiles are supported.
The transceiver interfaces directly to the antenna and
is fully compliant with the
Bluetooth 4.2
standard.
The DA14581 has dedicated hardware for the Link
Layer implementation of
Bluetooth low energy
and
interface controllers for enhanced connectivity capabili-
ties.
FINAL
Features
Complies with
Bluetooth V4.2,
ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan)
Supports up to 8 Bluetooth low energy connections
Fast cold boot in less than 30 ms
Processing power
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
face
________________________________________________________________________________________________
Dedicated Link Layer Processor
AES-128 bit encryption Processor
Memories
32 kB One-Time-Programmable (OTP) memory
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
Power management
Integrated Buck/Boost DC-DC converter
P0, P1 and P2 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
battery cells
10-bit ADC for battery voltage measurement
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
Gen. purpose I/Os: 14 (WLCSP34), 24 (QFN40)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
I2C bus at 100 kHz, 400 kHz
3-axes capable Quadrature Decoder
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
switching required
Supply current at VBAT3V:
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
0 dBm transmit output power
-20 dBm output power in “Near Field Mode”
-93 dBm receiver sensitivity
Packages:
WLCSP 34 pins, 2.436 mm x 2.436 mm
QFN 40 pins, 5 mm x 5 mm
System Diagram
Datasheet
CFR0011-120-01
Revision 3.1
1 of 152
10-Nov-2016
© 2015 Dialog Semiconductor
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 7
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 8
4.2 BLUETOOTH LOW ENERGY . . . . . . . . . . . . . . 8
4.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . . 9
4.2.3 SmartSnippets
4.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 10
4.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . .11
4.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . .11
4.6.4 General Purpose ADC . . . . . . . . . . . . . . 12
4.6.5 Quadrature Decoder . . . . . . . . . . . . . . . 12
4.6.6 Keyboard Controller . . . . . . . . . . . . . . . . 12
4.6.7 Input/Output Ports . . . . . . . . . . . . . . . . . 12
4.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7.1 General Purpose Timers . . . . . . . . . . . . 12
4.7.2 Wake-Up Timer . . . . . . . . . . . . . . . . . . . 13
4.7.3 Watchdog Timer. . . . . . . . . . . . . . . . . . . 13
4.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 14
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . 149
7.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 149
7.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 149
7.3 SOLDERING INFORMATION . . . . . . . . . . . . 149
7.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 150
FINAL
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.1
2 of 152
10-Nov-2016
© 2015 Dialog Semiconductor
DA14581
FINAL
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
1
Block Diagram
24 April 2012
XTAL
16 MHz
LDO
SYS
LDO
RET
LDO
LDO
LDO
SYS
SYS
RF
ARM Cortex M0
XTAL
32.768 kHz
RC
16 MHz
RC
32 kHz
DCDC
(BUCK/BOOST)
RCX
CORE
BLE Core
POReset
SWD (JTAG)
AES-128
LINK LAYER
HARDWARE
System/
Exchange
RAM
42 kB
Radio
Transceiver
Ret. RAM
2 kB
Ret. RAM3
2 kB
APB bridge
Ret. RAM2
3 kB
Ret. RAM4
1 kB
Timer 0
1xPWM
Timer 2
3xPWM
Memory Controller
SW TIMER
UART2
WAKE UP
TIMER
GP ADC
UART
SPI
I2C
FIFO
FIFO
KEYBOARD
CTRL
OTP
32 kB
OTPC
ROM
84 kB
POWER/CLOCK
Management (PMU)
GPIO MULTIPLEXING
Figure 1: DA14581 Block Diagram
Datasheet
Revision 3.1
3 of 152
FIFO
CFR0011-120-01
© 2015 Dialog Semiconductor
QUAD
DECODER
DMA
10-Nov-2016
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
2
Pinout
The DA14581 comes in two packages:
• A Wafer Level Chip Scale Package (WLCSP) with
34 balls
FINAL
• A Quad Flat Package No Leads (QFN) with 40 pins
The actual pin/ball assignment is depicted in the follow-
ing figures:
1
A
B
C
D
E
F
2
3
m
FI
O
4
R
FI
O
p
5
N
D
G
6
VP
P
XT
XT
AL
AL
16
16
M
M
m
p
VD
C
P1
D
C
_3
_R
F
R
P0
_1
LK
G
2
G
N
D
_C
2
D
IO
SW
G
N
D
D
P1
_1
P0
_4
SW
G
VB
AT
_R
F
VB
AT
1V
P1
_0
DA14581 (Top View)
Figure 2: WLCSP Ball Assignment
40
39
38
37
36
35
34
33
32
P0_0
P0_1
P0_2
P0_3
NC
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
VDCDC_RF
RFIOm
RFIOp
P2_9
P2_8
P2_6
P2_0
P2_7
P2_5
VPP
XT
AL
32
Kp
XT
AL
32
Km
H
C
VB
AT
3V
IT
C
D
VD
C
SW
G
N
D
P0
_7
P0
_6
R
ST
P0
_
N
5
P0
_
P1
_
P0
_
3
P0
_0
N
D
XTAL16Mm
XTAL16Mp
P1_3
P1_2
SW_CLK
SWDIO
P1_1
VBAT1V
P1_0
SWITCH
DA14581
(Top View)
26
25
24
23
22
21
VBAT_RF
VBAT3V
XTAL32Km
XTAL32Kp
P2_2
P2_3
Pin 0: GND
plane
Figure 3: QFN40 Pin Assignment
Datasheet
CFR0011-120-01
Revision 3.1
4 of 152
VDCDC
P2_4
GND
RST
10-Nov-2016
© 2015 Dialog Semiconductor
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
FINAL
Table 1: Pin Description
Pin Name
Type
Drive
(mA)
4.8
Reset
State
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
Description
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4/SWCLK
P1_5/SW_DIO
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_8
P2_9
P3_0 to P3_7
Debug interface
SWDIO/P1_5
SW_CLK/
P1_4
Clocks
XTAL16Mp
XTAL16Mm
XTAL32kp
XTAL32km
QD_CHA_X
QD_CHB_X
QD_CHA_Y
QD_CHB_Y
QD_CHA_Z
QD_CHB_Z
SPI Bus Interface
SPI_CLK
SPI_DI
SPI_DO
DO
DI
DO
INPUT/OUTPUT. SPI Clock. Mapped on Px ports
INPUT. SPI Data input. Mapped on Px ports
OUTPUT. SPI Data output. Mapped on Px ports
AI
AO
AI
AO
DI
DI
DI
DI
DI
DI
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
INPUT. Channel A for the X axis. Mapped on Px ports
INPUT. Channel B for the X axis. Mapped on Px ports
INPUT. Channel A for the Y axis. Mapped on Px ports
INPUT. Channel B for the Y axis. Mapped on Px ports
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
DIO
DIO
4.8
4.8
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
4.8
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
NOTE: This port is only available on the QFN40 package.
4.8
4.8
Not supported.
Quadrature Decoder
Datasheet
CFR0011-120-01
Revision 3.1
5 of 152
10-Nov-2016
© 2015 Dialog Semiconductor
京公网安备 11010802033920号
EEWORLD
