EU restricts the use of certain hazardous substances
Compliant
ECCN (US)
3A991.c.3
Part Status
Active
HTS
8542.39.00.01
Converter Type
General Purpose
Architecture
Pipelined
Resolution
14bit
Number of ADCs
2
Number of Input Channels
2
Sampling Rate
65Msps
Digital Interface Type
Parallel
Input Type
Voltage
Input Signal Type
Differential
Voltage Reference
Internal|External
Voltage Supply Source
Single
Input Voltage
1Vp-p/2Vp-p
Minimum Single Supply Voltage (V)
1.7
Typical Single Supply Voltage (V)
1.8
Maximum Single Supply Voltage (V)
1.9
Typical Power Dissipation (mW)
219
Maximum Power Dissipation (mW)
249
Integral Nonlinearity Error
±2.4LSB
Full Scale Error
-1.5/1.1%FSR
Signal to Noise Ratio
73.2dBFS(Typ)
No Missing Codes (bit)
14
Sample and Hold
Yes
Single-Ended Input
No
Digital Supply Support
No
Minimum Operating Temperature (°C)
-40
Maximum Operating Temperature (°C)
85
Packaging
Tape and Reel
Supplier Temperature Grade
Industrial
Supplier Package
QFN EP
Pin Count
64
Standard Package Name
QFN
Mounting
Surface Mount
Package Height
0.75(Max)
Package Length
9
Package Width
9
PCB changed
64
Lead Shape
No Lead
LTC2142IUP-14#TRPBF Preview
LTC2142-14/
LTC2141-14/LTC2140-14
14-Bit, 65Msps/
40Msps/25Msps Low Power
Dual ADCs
DESCRIPTION
The LTC
®
2142-14/LTC2141-14/LTC2140-14 are 2-channel
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.2dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.2LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
Two-Channel Simultaneously Sampling ADC
73.2dB SNR
90dB SFDR
Low Power: 95mW/67mW/50mW Total
48mW/34mW/25mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
750MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm × 9mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
TYPICAL APPLICATION
1.8V
V
DD
1.8V
OV
DD
2-Tone FFT, f
IN
= 70MHz and 69MHz
0
–10
–20
–30
AMPLITUDE (dBFS)
CMOS,
DDR CMOS,
OR
DDR LVDS
OUTPUTS
–40
–50
–60
–70
–80
CH 1
ANALOG
INPUT
S/H
14-BIT
ADC CORE
D1_13
D1_0
D2_13
CH 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
OUTPUT
DRIVERS
D2_0
–90
–100
–110
–120
0
5
10
15
20
FREQUENCY (MHz)
25
30
21421014 TA01b
65MHz
CLOCK
CLOCK
CONTROL
21421014 TA01a
GND
OGND
21421014fa
1
LTC2142-14/
LTC2141-14/LTC2140-14
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (V
DD
, OV
DD
) ....................... –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN –
,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2142C, LTC2141C, LTC2140C ............. 0°C to 70°C
LTC2142I, LTC2141I, LTC2140I ............–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
PIN CONFIGURATIONS
FULL RATE CMOS OUTPUT MODE
TOP VIEW
64 V
DD
63 SENSE
62 V
REF
61 SDO
60 OF1
59 OF2
58 D1_13
57 D1_12
56 D1_11
55 D1_10
54 D1_9
53 D1_8
52 D1_7
51 D1_6
50 D1_5
49 D1_4
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
64 V
DD
63 SENSE
62 V
REF
61 SDO
60 OF2_1
59 DNC
58 D1_12_13
57 DNC
56 D1_10_11
55 DNC
54 D1_8_9
53 DNC
52 D1_6_7
51 DNC
50 D1_4_5
49 DNC
48 D1_3
47 D1_2
46 D1_1
45 D1_0
44 DNC
43 DNC
42 OV
DD
41 OGND
40 CLKOUT
+
39 CLKOUT
–
38 D2_13
37 D2_12
36 D2_11
35 D2_10
34 D2_9
33 D2_8
V
DD
1
V
CM1
2
GND 3
A
IN1+
4
A
IN1–
5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
A
IN2+
12
A
IN2–
13
GND 14
V
CM2
15
V
DD
16
65
GND
48 D1_2_3
47 DNC
46 D1_0_1
45 DNC
44 DNC
43 DNC
42 OV
DD
41 OGND
40 CLKOUT
+
39 CLKOUT
–
38 D2_12_13
37 DNC
36 D2_10_11
35 DNC
34 D2_8_9
33 DNC
T
JMAX
= 150°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
V
DD
17
ENC
+
18
ENC
–
19
CS
20
SCK 21
SDI 22
DNC 23
DNC 24
DNC 25
D2_0_1 26
DNC 27
D2_2_3 28
DNC 29
D2_4_5 30
DNC 31
D2_6_7 32
UP PACKAGE
64-LEAD (9mm 9mm) PLASTIC QFN
V
DD
1
V
CM1
2
GND 3
A
IN1+
4
A
IN1–
5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
A
IN2+
12
A
IN2–
13
GND 14
V
CM2
15
V
DD
16
65
GND
T
JMAX
= 150°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
V
DD
17
ENC
+
18
ENC
–
19
CS
20
SCK 21
SDI 22
DNC 23
DNC 24
D2_0 25
D2_1 26
D2_2 27
D2_3 28
D2_4 29
D2_5 30
D2_6 31
D2_7 32
UP PACKAGE
64-LEAD (9mm 9mm) PLASTIC QFN
21421014fa
2
LTC2142-14/
LTC2141-14/LTC2140-14
PIN CONFIGURATIONS
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
64 V
DD
63 SENSE
62 V
REF
61 SDO
60 OF2_1
+
59 OF2_1
–
58 D1_12_13
+
57 D1_12_13
–
56 D1_10_11
+
55 D1_10_11
–
54 D1_8_9
+
53 D1_8_9
–
52 D1_6_7
+
51 D1_6_7
–
50 D1_4_5
+
49 D1_4_5
–
V
DD
1
V
CM1
2
GND 3
A
IN1+
4
A
IN1–
5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
A
IN2+
12
A
IN2–
13
GND 14
V
CM2
15
V
DD
16
65
GND
48 D1_2_3
+
47 D1_2_3
–
46 D1_0_1
+
45 D1_0_1
–
44 DNC
43 DNC
42 OV
DD
41 OGND
40 CLKOUT
+
39 CLKOUT
–
38 D2_12_13
+
37 D2_12_13
–
36 D2_10_11
+
35 D2_10_11
–
34 D2_8_9
+
33 D2_8_9
–
T
JMAX
= 150°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2142CUP-14#PBF
LTC2142IUP-14#PBF
LTC2141CUP-14#PBF
LTC2141IUP-14#PBF
LTC2140CUP-14#PBF
LTC2140IUP-14#PBF
TAPE AND REEL
LTC2142CUP-14#TRPBF
LTC2142IUP-14#TRPBF
LTC2141CUP-14#TRPBF
LTC2141IUP-14#TRPBF
LTC2140CUP-14#TRPBF
LTC2140IUP-14#TRPBF
PART MARKING*
LTC2142UP-14
LTC2142UP-14
LTC2141UP-14
LTC2141UP-14
LTC2140UP-14
LTC2140UP-14
PACKAGE DESCRIPTION
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
V
DD
17
ENC
+
18
ENC
–
19
CS
20
SCK 21
SDI 22
DNC 23
DNC 24
D2_0_1
–
25
D2_0_1
+
26
D2_2_3
–
27
D2_2_3
+
28
D2_4_5
–
29
D2_4_5
+
30
D2_6_7
–
31
D2_6_7
+
32
UP PACKAGE
64-LEAD (9mm 9mm) PLASTIC QFN
21421014fa
3
LTC2142-14/
LTC2141-14/LTC2140-14
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
LTC2142-14
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
Internal Reference
External Reference
Differential Analog Input
(Note 7)
Internal Reference
External Reference
CONDITIONS
l
LTC2141-14
MIN
14
–2.4
–0.8
–9
–1.5
TYP
±1
±0.3
±1.5
±1.5
–0.3
±10
±30
±10
±0.2
±1.5
1.31
MAX
2.4
0.8
9
1.1
14
LTC2140-14
MIN
–2.4
–0.8
–9
–1.5
TYP
±1
±0.3
±1.5
±1.5
–0.3
±10
±30
±10
±0.2
±1.5
1.19
MAX
2.4
0.8
9
1.1
UNITS
Bits
LSB
LSB
mV
%FS
%FS
μV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
MIN
14
–2.4
–0.8
–9
–1.5
TYP
±1
±0.3
±1.5
±1.5
–0.3
±10
±30
±10
±0.2
±1.5
1.23
MAX
2.4
0.8
9
1.1
Differential Analog Input (Note 6)
l
l
l
l
ANALOG INPUT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
0 < A
IN+
, A
IN–
< V
DD
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
Single-Ended Encode
Differential Encode
Figure 6 Test Circuit
l
l
l
l
l
l
MIN
0.7
0.625
TYP
1 to 2
V
CM
1.250
81
50
31
MAX
1.25
1.300
UNITS
V
P-P
V
V
μA
μA
μA
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
External Voltage Reference Applied to SENSE External Reference Mode
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
–1.5
–3
–3
0
0.08
0.10
80
750
1.5
3
3
μA
μA
μA
ns
ps
RMS
ps
RMS
dB
MHz
21421014fa
4
LTC2142-14/
LTC2141-14/LTC2140-14
DYNAMIC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2142-14
CONDITIONS
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
LTC2141-14
MIN
71.5
TYP
72.8
72.8
72.7
72.4
90
90
89
84
90
90
89
84
95
95
95
95
72.7
72.7
72.5
72
–110
MAX
LTC2140-14
MIN
72
TYP
73.7
73.7
73.6
73.2
90
90
89
84
90
90
89
84
95
95
95
95
73.5
73.5
73.4
72.7
–110
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MIN
71.8
TYP
73.2
73.2
73.1
72.7
90
90
89
84
90
90
89
84
95
95
95
95
73.1
73.1
72.9
72.2
–110
MAX
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
30MHz Input
70MHz Input
140MHz Input
l
79
81
81
l
82
82
82
l
86
86
88
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
10MHz Input
l
71.5
71.1
71.8
Crosstalk
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400μA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600μA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
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Embedded System
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