®
SP9601
12–Bit, Low Power Voltage Output D/A Converter
s
s
s
s
Low Power — 2mW
Voltage Output, 4.5V range
Midscale Preset, Zero Volts Out
250KHz Multiplying Bandwidth
(4-Quadrant)
s
Standard 3-Wire Serial Interface
s
8–pin (0.15") SOIC and Plastic DIP
Packages
s
±5V
supply operation
DESCRIPTION…
The
SP9601
is a very low power 12-Bit Digital-to-Analog Converter. It features
±4.5V
output
swings when using
±5
volt supplies. The converter uses a standard 3–wire serial interface
compatible with SPI
™
, QSPI
™
and Microwire
™
. The output settling-time is specified at 30µs. The
SP9601
is available in 8–pin 0.15" SOIC and DIP packages, specified over commercial and
industrial temperature ranges.
Ref In
DAC
REGISTER
LATCH
DAC
–
+
V
OUT
SHIFT
REGISTER
CS
SDI
SCK
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
© Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD
- GND ..................................................................... -0.3V,+6.0V
V
SS
- GND .................................................................... +0.3V, -6.0V
V
DD
- V
SS ......................................................................................................................
-0.3V, +12.0V
V
REF
..................................................................................... V
SS
, V
DD
D
IN
....................................................................................... V
SS
, V
DD
Power Dissipation
Plastic DIP .......................................................................... 375mW
(derate 7mW/°C above +70°C)
Plastic LCC ......................................................................... 375mW
(derate 7mW/˚C above +70˚C)
Small Outline ...................................................................... 375mW
(derate 7mW/˚C above +70˚C)
SPECIFICATIONS
(Typical at 25˚C; T
MIN
≤
T
A
≤T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
DIGITAL INPUTS
Logic Levels
V
IH
V
IL
4 Quad, Bipolar Coding
REFERENCE INPUT
Voltage Range
Input Resistance
ANALOG OUTPUT
Gain
-B, -K
-A, -J
Initial Offset Bipolar
Voltage Range Bipolar
Output Current
STATIC PERFORMANCE
Resolution
Integral Linearity
-B, -K
-A, -J
Differential Linearity
-B, -K
-A, -J
Monotonicity
DYNAMIC PERFORMANCE
Settling Time
Small Signal
Full Scale
Slew Rate
Multiplying Bandwidth
STABILITY
Gain
Bipolar Zero
MIN.
TYP.
MAX.
UNITS
CONDITIONS
2.4
0.8
Offset Binary
±3
8.8
±4.5
Volts
Volts
6
Volts
kΩ
Note 5
D
IN
= 1,877; code dependent
V
REF
=
±3V;
Note 3
V
REF
=
±3V;
Note 3
V
REF
=
±4.5V;
Note 3
D
IN
= 2,048
V
REF
=
±3V
V
REF
=
±4.5V
±5.0
±0.5
12
±0.5
±1.0
±1.0
±0.25
±3.0
±2.0
±4.0
±5.0
±3.0
±4.5
LSB
LSB
LSB
LSB
Volts
mA
mA
Bits
±0.25
±0.5
±0.5
±0.5
±1.0
±3.0
LSB
LSB
LSB
LSB
LSB
V
REF
=
±3V;
Note 3
V
REF
=
±3V;
Note 3
V
REF
=
±4.5V;
Note 3
±0.25
±0.75
±0.25
±1.0
Guaranteed
4
30
0.3
250
15
15
µs
µs
V/µs
KHz
ppm/˚C
ppm/˚C
to 0.024%
to 0.024%
t
MIN
to t
MAX
t
MIN
to t
MAX
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
© Copyright 2000 Sipex Corporation
2
SPECIFICATIONS
(continued)
(Typical at 25˚C; T
MIN
≤
T
A
≤T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
POWER REQUIREMENTS
V
DD
-J, -K
-A, -B
V
SS
-J, -K
-A, -B
Power Dissipation
SWITCHING
CHARACTERISTICS
CS Setup Time
(t
CSS
)
SCLK Fall to CS
Fall Hold Time
(t
CSH0
)
SCLK Fall to CS Rise
Hold Time
(t
CSH1
)
SCLK High Width
(t
CH
)
SCLK Low Width
(t
CL
)
DIN Setup Time
(t
DS
)
DIN Hold Time
(t
DH
)
CS High Pulse Width
(t
CSW
)
ENVIRONMENTAL AND
MECHANICAL
Operating Temperature
-J, -K
-A, -B
Storage
Package
–_N
–_S
Notes:
1.
2.
3.
4.
5.
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Note 5
+5V,
±3%;
Note 4, 5
-5V,
±3%;
Note 4, 5
0.2
0.2
0.2
0.2
2
0.3
0.45
0.3
0.45
mA
mA
mA
mA
mW
25
ns
20
ns
0
40
40
50
0
30
ns
ns
ns
ns
ns
ns
0
-40
-60
+70
+85
+150
8-pin Plastic DIP
8-pin 0.15" SOIC
°C
°C
°C
Integral Linearity, for the
SP9601,
is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*V
REF
/4,096.
V
REF
= 0V.
The following power up sequence is recommended: V
SS
(-5V), Vdd (+5V), V
REF
.
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
© Copyright 2000 Sipex Corporation
3
PINOUT – 8-PIN PLASTIC DIP & SOIC
THEORY OF OPERATION
The
SP9601
consists of four main functional
blocks – the input shift register, DAC register,
12-Bit D/A converter and a bipolar output volt-
age amplifier,
Figure 1.
The input shift register is used to convert the
serial input data stream to a parallel 12–Bit
digital word. The input data is shifted on posi-
tive clock (SCLK) edges when the Chip Select
(CS) signal is in the “low” state. The MSB is
loaded first and LSB last. No shifting of the
input data occurs when the Chip Select (CS)
signal is in the “high” state.
The DAC register is used to store the digital
word which is sent to the DAC. Its value is
updated on the positive transition of the Chip
Select (CS) signal.
In order to reduce the DAC full scale output
sensitivity to the large weighting of the MSB's
found in conventional R-2R resistor ladders, the
3 MSB's are decoded into 8 equally weighted
levels. This reduces the contribution of each bit
by a factor of 4, thus, reducing the output sensi-
tivity to mismatches in resistors and switches by
the same amount. Linearity errors and stability
are both improved for the same reasons.
The DAC itself is implemented with precision
thin-film resistors and CMOS transmission gate
switches. The resistor network is laser-trimmed
to achieve better than 12–Bit accuracy. The D/
A converter is used to convert the 12-bit input
word to a precision voltage.
V
OUT
V
DD
SCLK
D
IN
1
2
3
4
8
7
V
REF
GND
V
SS
CS
SP9601
6
5
PIN ASSIGNMENTS
Pin 1- V
OUT
– Voltage Output.
Pin 2- V
DD
– +5V Power Supply Input.
Pin 3- SCLK – Serial Clock Input.
Pin 4- D
IN
– Serial Data Input.
Pin 5- CS – Chip Select Input.
Pin 6- V
SS
– –5V Power Supply Input.
Pin 7- GND – Ground.
Pin 8- V
REF
– Reference Input.
FEATURES...
The
SP9601
is a low power 12–Bit Digital-to-
Analog Converter. The converter features
±4.5V
output swings with
±5V
supplies. The input
coding format used is standard offset binary,
Table 1.
This Digital-to Analog Converter uses a stan-
dard 3–wire interface compatible with SPI
™
,
QSPI
™
and Microwire
™
. The output settling
time is specified at 30µs to full 12-bit accuracy
when driving a 5KΩ, 50pF load combination.
The
SP9601
Digital-to-Analog Converter is
ideally suited for applications such as ATE,
process controllers, robotics and instrumenta-
tion. The
SP9601
is available in an 8-pin 0.15"
SOIC and 0.3" PDIP packages, specified over
commercial and industrial temperature ranges.
INPUT
MSB
1111
1111
1000
1000
0000
0000
1111
1111
0000
0000
0000
0000
LSB
1111
1110
0001
0000
0001
0000
1 LSB =
Table 1. Offset Binary Coding
2
12
OUTPUT
V
REF
- 1 LSB
V
REF
- 2 LSB
0 + 1 LSB
0
-V
REF
+ 1 LSB
-V
REF
2 V
REF
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
© Copyright 2000 Sipex Corporation
4
V
REF
DAC
REGISTER
D
IN
1
40KΩ 40KΩ
3 TO 7
DECODE
–
+
SHIFT
REGISTER
12
3
7
9
16
DAC
V
OUT
LATCH
9
Figure 1. Detailed Block Diagram
The operational amplifier is a rail-to-rail input,
rail-to-rail output CMOS amplifier. It is capable
of supplying 5mA of load current in the
±3
volt
output range. The initial offset voltage is laser-
trimmed to improve accuracy. Settling time is
30µs for a full scale output transition to 0.024%
accuracy.
The bipolar voltage output of the
SP9601
is
created on chip from the DAC output voltage
(V
DAC
) by using an operational amplifier and
two feedback resistors connected as shown in
Figure 2. This configuration produces a
±4.5V
bipolar output range with standard offset binary
coding,
Table 1.
USING THE SP9601
External Reference
The DAC input resistance is code dependent
and is minimum at code 1877 and nearly infinite
at code 0. Because of the code-dependent nature
of the reference a high quality, low output im-
pedance amplifier should be used to drive the
V
REF
input.
Serial Clock and Update Rate
The
SP9601
maximum serial clock rate (SCLK)
is given by 1/(t
CH
+t
CL
) which is approximately
V
REF
12.5 MHz. The digital word update rate is lim-
ited by the chip select period, which is 12 X
SCLK periods plus the CS high pulse width t
CSW
.
This is equal to a 1
µs
or 1 MHz update rate.
However, the DAC settling time to 12–Bits is 30
µs,
which for full scale output transitions would
limit the update rate to 33 kHz.
Logic Interface
The
SP9601
is designed to be compatible with
TTL and CMOS logic levels. However, driving
the digital inputs with TTL level signals will
increase the power consumption of the part by
300
µA.
In order to achieve the lowest power
consumption use rail-to-rail CMOS levels to
drive the digital inputs.
Midscale Preset
By holding CS pin low during Power-up, the
DAC output can be forced to 0V. Following
Power-up, the CS pin should be kept low as the
first digital word is shifted into the shift register.
When CS pin is set high, the digital word in the
shift register (loaded by the last 12 clock cycles)
is latched into the DAC register. Thus, the DAC
can be forced to go from midscale (1000 0000
0000, on Power-up) to any digital state, without
entering an unknown state.
WHERE
V
OUT
=
V
OUT
V
DAC
=
D
IN
–
+
V
DAC
(
(
D
IN
2048
D
IN
4096
– 1 x V
REF
)
)
x V
REF
Figure 2. Transfer Function
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
© Copyright 2000 Sipex Corporation
5
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