FEATURES
■
■
■
■
■
■
■
■
■
■
■
LTC4264
High Power PD Interface
Controller with 750mA
Current Limit
DESCRIPTION
The LTC
®
4264 is an integrated Powered Device (PD) in-
terface controller intended for IEEE 802.3af Power over
Ethernet (PoE) and high power PoE applications up to 35W.
By including a precision dual current limit, the LTC4264
keeps inrush below the IEEE802.3af current limit levels
to ensure interoperability success while allowing for high
power PD operation. The LTC4264 includes a field-proven
power MOSFET delivering up to 750mA to the PD load while
maintaining compliance with the IEEE802.3af standard.
Complementary power good outputs allow the LTC4264 to
interface directly with a host of DC/DC converter products.
The LTC4264 provides a complete signature and power
interface solution for PD designs by incorporating the 25k
signature resistor, classification circuitry, input current
limit, undervoltage lockout, thermal overload protection,
signature disable and power good signaling.
The LTC4264 PD interface controller can be used along with
a variety of Linear Technology DC/DC converter products
to provide a complete, cost effective power solution for
high power PD applications.
The LTC4264 is available in the space-saving low profile
(4mm
×
3mm) DFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Complete High Power PD Interface Controller
IEEE 802.3af
®
Compliant
Onboard 750mA Power MOSFET
Complementary Power Good Outputs
Flexible Auxiliary Power Options
Precision Dual Current Limit with Disable
Programmable Classification Current to 75mA
Onboard 25k Signature Resistor with Disable
Undervoltage Lockout
Complete Thermal Overload Protection
Available in Low Profile (4mm
×
3mm) DFN Package
APPLICATIONS
■
■
■
■
802.11n Access Points
High Power VoIP Video Phones
RFID Reader Systems
PTZ Security Cameras and Surveillance Equipment
TYPICAL APPLICATION
Turn On vs Time
V
IN
50V/DIV
C
LOAD
= 100µF
–54V FROM
DATA PAIR
~
~
~
+
0.1µF
SMAJ58A
DF1501S
–
+
–
LTC4264
SHDN
GND
R
CLASS
PWRGD
R
CLASS
I
LIM_EN
V
IN
V
OUT
PWRGD
5µF
MIN
+
–54V FROM
SPARE PAIR
DF1501S
V
IN
SWITCHING
POWER
SUPPLY
RUN
RTN
V
OUT
50V/DIV
+
3.3V
TO LOGIC
PWRGD – V
OUT
50V/DIV
I
IN
200mA/DIV
TIME (5ms/DIV)
4264 TA01b
~
4264 TA01a
–
4264f
1
LTC4264
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW
SHDN
NC
R
CLASS
I
LIM_EN
V
IN
V
IN
1
2
3
4
5
6
13
12 GND
11 NC
10 PWRGD
9
8
7
PWRGD
V
OUT
V
OUT
V
IN
Voltage ................................................. 0.3V to –90V
V
OUT
Voltage ......... V
IN
+ 90V (and ≤ GND) to V
IN
– 0.3V
SHDN Voltage ............................ V
IN
+ 90V to V
IN
– 0.3V
R
CLASS
, I
LIM_EN
Voltage ............... V
IN
+ 7V to V
IN
– 0.3V
PWRGD Voltage (Note 3)
Low Impedance Source ....V
OUT
+ 11V to V
OUT
– 0.3V
Current Fed ..........................................................5mA
PWRGD Voltage ......................... V
IN
+ 80V to V
IN
– 0.3V
PWRGD Current .....................................................10mA
R
CLASS
Current.....................................................100mA
Operating Ambient Temperature Range
LTC4264C ................................................ 0°C to 70°C
LTC4264I ............................................. –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
DE12 PACKAGE
12-LEAD (4mm
×
3mm) PLASTIC DFN
T
JMAX
= 150°C,
θ
JA
= 43°C/W,
θ
JC
= 4.3°C/W
EXPOSED PAD (PIN 13) MUST BE SOLDERED TO
AN ELECTRICALLY ISOLATED HEAT SINK
ORDER PART NUMBER
LTC4264CDE
LTC4264IDE
DE PART MARKING*
4264
4264
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
SYMBOL
V
IN
PARAMETER
Supply Voltage
IEEE 802.3af System
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
IC Supply Current when On
IC Supply Current During Classification
Current Accuracy During Classification
Classification Stability Time
Signature Resistance
Invalid Signature Resistance
SHDN High Level Input Voltage
SHDN Low Level Input Voltage
SHDN Input Resistance
I
LIM_EN
High Level Input Voltage
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
CONDITIONS
Voltage with Respect to GND Pin
(Notes 5, 6, 7, 8)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
MIN
TYP
MAX
–57
–10.1
–21
–40.2
–31.5
3
0.70
±3.5
1
UNITS
V
V
V
V
V
mA
mA
%
ms
kΩ
kΩ
V
V
kΩ
V
4264f
–1.5
–12.5
–37.7
–29.8
0.55
–38.9
–30.6
0.62
I
IN_ON
I
IN_CLASS
ΔI
CLASS
t
CLASSRDY
R
SIGNATURE
R
INVALID
V
IH_SHDN
V
IL_SHDN
R
INPUT_SHDN
V
IH_ILIM
V
IN
= –54V
V
IN
= –17.5V (Note 9)
10mA < I
CLASS
< 75mA, –12.5V ≤ V
IN
≤ –21V
(Notes 10,11)
V
IN
Stepped 0V to –17.5V, I
IN_CLASS
≤3.5% of
Ideal, 10mA < I
CLASS
< 75mA (Notes 10, 11)
–1.5V ≤ V
IN
≤ –10.1V, IEEE 802.3af 2-Point
Measurement, SHDN Tied to V
IN
(Notes 6, 7)
–1.5V ≤ V
IN
≤ –10.1V, IEEE 802.3af 2-Point
Measurement, SHDN Tied to GND (Notes 6, 7)
With Respect to V
IN
, High Level = Shutdown
(Note 12)
With Respect to V
IN
With Respect to V
IN
With Repect to V
IN
, High Level Enables Current
Limit (Note 13)
23.25
10
3
26.00
11.8
57
0.45
100
4
2
LTC4264
ELECTRICAL CHARACTERISTICS
SYMBOL
V
IL_ILIM
V
PWRGD_OUT
I
PWRGD_LEAK
V
PWRGD_OUT
PARAMETER
I
LIM_EN
Low Level Input Voltage
Active Low Power Good
Output Low Voltage
Active Low Power Good Leakage
Active High Power Good
Output Low Voltage
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
CONDITIONS
With Respect to V
IN
(Note 13)
I
PWRGD
= 1mA, V
IN
= –54V,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D
Referenced to V
IN
V
IN
= 0V, V
PWRGD
= 57V
I
PWRGD
= 0.5mA, V
IN
= –52V, V
OUT
= –4V,
PWRGD Referenced to V
OUT
(Note 14)
I
PWRGD
= 2mA, V
OUT
= 0V,
With Respect to V
OUT
(Note 3)
V
PWRGD
= 11V, with Respect to V
OUT
,
V
OUT
= V
IN
= –54V
I = 700mA, V
IN
= –54V
Measured from V
IN
to V
OUT
(Note 11)
V
IN
= –57V, GND = SHDN = V
OUT
= 0V
V
IN
= –54V, V
OUT
= –53V, I
LIM_EN
Floating
(Notes 15, 16)
V
IN
= –54V, V
OUT
= –53V (Notes 15, 16)
V
IN
= –54V, V
OUT
= –52.5V, I
LIM_EN
Tied to V
IN
(Notes 15, 16, 17)
●
●
●
●
●
●
MIN
TYP
MAX
1
0.5
1
0.35
UNITS
V
V
µA
V
V
µA
Ω
Ω
µA
mA
mA
A
V
PWRGD_VCLAMP
Active High Power Good
Voltage-Limiting Clamp
I
PWRGD_LEAK
R
ON
I
OUT_LEAK
I
LIMIT_HIGH
I
LIMIT_LOW
I
LIMIT_DISA
Active High Power Good Leakage
On Resistance
V
OUT
Leakage
Input Current Limit During Normal
Operation
Inrush Current Limit
Safeguard Current Limit when
I
LIMIT_HIGH
Disabled
12.0
14.0
16.5
1
●
●
●
●
0.5
0.6
0.8
1
800
350
1.65
700
250
1.20
750
300
1.45
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
Note 2:
All voltages are with respect to GND pin unless otherwise noted.
Note 3:
Active high PWRGD pin internal clamp circuit self-regulates to 14V
with respect to V
OUT
.
Note 4:
The LTC4264 operates with a negative supply voltage in the range of
–1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5:
In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V. See Applications Information.
Note 6:
The LTC4264 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specified in the Electrical
Characteristics are with respect to LTC4264 pins and are designed to meet
IEEE 802.3af specifications when the drop from the two diodes is included.
See Applications Information.
Note 7:
Signature resistance is measured via the two-point
ΔV/ΔI
method
as defined by IEEE 802.3af. The LTC4264 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4264 pins
are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V.
Note 8:
The LTC4264 includes hysteresis in the UVLO voltages to preclude
any start-up oscillation. Per IEEE 802.3af requirements, the LTC4264 will
power up from a voltage source with 20Ω series resistance on the first trial.
Note 9:
I
IN_CLASS
does not include classification current programmed at
Pin 3. Total supply current in classification mode will be I
IN_CLASS
+ I
CLASS
(see Note 10).
Note 10:
I
CLASS
is the measured current flowing through R
CLASS
.
ΔI
CLASS
accuracy is with respect to the ideal current defined as I
CLASS
= 1.237/R
CLASS
.
t
CLASSRDY
is the time for I
CLASS
to settle to within ±3.5% of ideal. The current
accuracy specification does not include variations in R
CLASS
resistance. The
total classification current for a PD also includes the IC quiescent current
(I
IN_CLASS
). See Applications Information.
Note 11:
This parameter is assured by design and wafer level testing.
Note 12:
To disable the 25k signature, tie SHDN to GND (±0.1V) or hold SHDN
pin high with respect to V
IN
. See Applications Information.
Note13:
I
LIM_EN
pin is pulled high internally and for normal operation should
be left floating. To disable high level current limit, tie I
LIM_EN
to V
IN
. See
Applications Information.
Note 14:
Active high power good is referenced to V
OUT
and is valid for
GND-V
OUT
≥ 4V. Measured at –52V due to test hardware limitations.
Note 15:
The LTC4264 includes a dual current limit. At turn-on, before C1 is
charged, the LTC4264 current level is set to I
LIMIT_LOW
. After C1 is charged
and with I
LIM_EN
floating, the LTC4264 switches to I
LIMIT_HIGH
. With I
LIM_EN
pin tied low, the LTC4264 switches to I
LIMIT_DISA
. The LTC4264 stays in
I
LIMIT_HIGH
or I
LIMIT_DISA
until the input voltage drops below the UVLO turn-
off threshold or a thermal overload occurs.
Note 16:
The LTC4264 features thermal overload protection. In the event of
an overtemperature condition, the LTC4264 will turn off the power MOSFET,
disable the classification load current and present an invalid power good
signal. Once the LTC4264 cools below the overtemperature limit, the
LTC4264 current limit switches to I
LIMIT_LOW
and normal operation resumes.
Thermal overload protection is intended to protect the device during
momentary fault conditions and continuous operation in thermal overload
should be avoided as it may impair device reliability.
Note 17:
I
LIMIT_DISA
is a safeguard current limit that is activated when the
normal input current limit (I
LIMIT_HIGH
) is defeated using the I
LIM_EN
pin.
Currents at or near I
LIMIT_DISA
will cause significant package heating and may
require a reduced maximum ambient operating temperature in order to avoid
tripping the thermal overload protection. See Applications Information.
4264f
3
LTC4264
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
0.5
100
T
A
= 25°C
80
INPUT CURRENT (mA)
CLASS 5*
60
CLASS 4
40
CLASS 3
20
CLASS 2
CLASS 1
CLASS 0
0
0
0
–2
–4
–6
INPUT VOLTAGE (V)
–8
–10
4264 G01
Input Current vs Input Voltage
T
A
= 25°C
12.0
11.5
INPUT CURRENT (mA)
11.0
10.5
10.0
9.5
Input Current vs Input Voltage
CLASS 1 OPERATION
0.4
INPUT CURRENT (mA)
0.3
85°C
–40°C
0.2
0.1
0
– 20
–30
–40
INPUT VOLTAGE (V)
*OPTIONAL CLASS CURRENT
–10
–50
–60
9.0
–12
–14
–20
–18
–16
INPUT VOLTAGE (V)
–22
4264 G03
4264 G02
Signature Resistance
vs Input Voltage
28
RESISTANCE =
∆V
= V2 – V1
∆I
I
2
– I
1
27 DIODES: HD01
T
A
= 25°C
IEEE UPPER LIMIT
INPUT
VOLTAGE
10V/DIV
Class Operation vs Time
1.0
T
A
= 25°C
0.8
RESISTANCE (Ω)
On Resistance vs Temperature
SIGNATURE RESISTANCE (kΩ)
26
25
24
LTC4264 ONLY
23
22
V1: –1
V2: –2
IEEE LOWER LIMIT
LTC4264 + 2 DIODES
CLASS
CURRENT
20mA/DIV
0.6
0.4
0.2
–3
–4
–7
–5
–8
–6
INPUT VOLTAGE (V)
–9
–10
4264 G04
TIME (10µs/DIV)
4264 G05
0
–50
0
25
50
75
–25
JUNCTION TEMPERATURE (°C)
100
4264 G06
Active Low PWRGD
Output Low Voltage vs Current
4
1.0
T
A
= 25°C
0.8
V
PWRGD_OUT
– V
IN
(V)
Active High PWRGD
Output Low Voltage vs Current
T
A
= 25°C
GND – V
OUT
= 4V
CURRENT LIMIT (mA)
800
Current Limit vs Input Voltage
–40°C
85°C
HIGH CURRENT MODE
600
3
PWRGD (V)
0.6
2
0.4
400
–40°C
85°C
LOW CURRENT MODE
1
0.2
0
0
0
2
6
4
CURRENT (mA)
8
10
4264 G07
0
0.5
1
I
IN
(mA)
1.5
2
4264 G08
200
–40
–55
–45
–50
INPUT VOLTAGE (V)
–60
4264 G09
4264f
4
LTC4264
PIN FUNCTIONS
SHDN (Pin 1):
Shutdown Input. Used to command the
LTC4264 to present an invalid signature. Connecting
SHDN to GND lowers the signature resistance to an invalid
value and disables other LTC4264 operations. If unused,
tie SHDN to V
IN
.
NC (Pin 2):
No Internal Connection.
R
CLASS
(Pin 3):
Class Select Input. Used to set the current
the LTC4264 maintains during classification. Connect a
resistor between R
CLASS
and V
IN
. (See Table 2.)
I
LIM_EN
(Pin 4):
Input Current Limit Enable. Used to control
LTC4264 current limit behavior during powered operation.
For normal operation, float I
LIM_EN
to enable I
LIMIT_HIGH
current. Tie I
LIM_EN
to V
IN
to disable input current limit.
Note that the inrush current limit does not change with
I
LIM_EN
selection. See Applications Information.
V
IN
(Pins 5, 6):
Power Input. Tie to the PD input through
the diode bridge. Pins 5 and 6 must be electrically tied
together.
V
OUT
(Pins 7, 8):
Power Output. Supplies power to the
PD load through the internal power MOSFET. V
OUT
is high
impedance until the input voltage rises above the UVLO
turn-on threshold. The output is then connected to V
IN
through a current-limited internal MOSFET switch. Pins 7
and 8 must be electrically tied together.
PWRGD (Pin 9):
Active High Power Good Output, Open
Collector. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
High impedance indicates power is good. PWRGD is ref-
erenced to V
OUT
and is low impedance during inrush and
in the event of a thermal overload. PWRGD is clamped
14V above V
OUT
.
PWRGD (Pin 10):
Active Low Power Good Output, Open-
Drain. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
Low impedance indicates power is good. PWRGD is
referenced to V
IN
and is high impedance during detec-
tion, classification and in the event of a thermal overload.
PWRGD has no internal clamps.
NC (Pin11):
No Internal Connection.
GND (Pin 12):
Ground. Tie to system ground and power
return through the input diode bridge.
Exposed Pad (Pin 13):
Must be soldered to electrically
isolated heat sink.
4264f
5
Embedded System
京公网安备 11010802033920号
EEWORLD
