UVLO, SYNC Voltage...................................–0.3V to V
CC
FB Current ..............................................................±2mA
V
CMP
Current .........................................................±1mA
Operating Ambient Temperature Range
LTC4269C-1 ................................................. 0°C to 70°C
LTC4269I-1 .............................................. –40°C to 85°C
V
CC
10
t
ON
11
ENDLY 12
SYNC 13
SFST 14
OSC 15
FB 16
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 34°C/W,
θ
JC
= 2°C/W
GND, EXPOSED PAD (PIN 33) MUST BE SOLDERED TO A
HEAT SINKING PLANE THAT IS CONNECTED TO V
NEG
ORDER INFORMATION
LEAD FREE FINISH
LTC4269CDKD-1#PBF
LTC4269IDKD-1#PBF
TAPE AND REEL
LTC4269CDKD-1#TRPBF
LTC4269IDKD-1#TRPBF
PART MARKING*
42691
42691
PACKAGE DESCRIPTION
32-Lead (7mm
×
4mm) Plastic DFN
32-Lead (7mm
×
4mm) Plastic DFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
42691fc
2
LTC4269-1
ELECTRICAL CHARACTERISTICS
PARAMETER
Interface Controller (Note 4)
Operating Input Voltage
Signature Range
Classification Range
ON Voltage
OFF Voltage
Overvoltage Lockout
ON/OFF Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
Supply Current
Supply Current at 57V
Class 0 Current
Signature
Signature Resistance
Invalid Signature Resistance, SHDN Invoked
Classification
Class Accuracy
Classification Stability Time
Normal Operation
Inrush Current
Power FET On-Resistance
Power FET Leakage Current at V
NEG
Digital Interface
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
PWRGD, T2P
Output Low Voltage
PWRGD, T2P
Leakage Current
PWRGD Output Low Voltage
PWRGD Clamp Voltage
PWRGD Leakage Current
V
PORTP
= 9.8V, SHDN = 9.65V
Tested at 1mA, V
PORTP
= 54V. For
T2P,
Must Complete
2-Event Classification to See Active Low
Pin Voltage Pulled 57V, V
PORTP
= V
PORTN
= 0V
Tested at 0.5mA, V
PORTP
= 52V, V
NEG
= 48V, Output
Voltage Is with Respect to V
NEG
Tested at 2mA, V
NEG
= 0V, Voltage with Respect to V
NEG
V
PWRGD
= 11V, V
NEG
= 0V, Voltage with Respect to V
NEG
l
l
l
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
CONDITIONS
At V
PORTP
(Note 5)
MIN
TYP
MAX
60
9.8
21
37.2
71
l
l
l
l
l
l
l
l
l
l
UNITS
V
V
V
V
V
V
V
V
l
l
l
l
1.5
12.5
30.0
4.1
1.4
2.57
State Machine Reset for 2-Event Classification
Measured at V
PORTP
Pin
V
PORTP
= 17.5V, No R
CLASS
Resistor
1.5V ≤ V
PORTP
≤ 9.8V (Note 6)
1.5V ≤ V
PORTP
≤ 9.8V, V
SHDN
= 3V (Note 6)
5.40
1.35
0.40
V
mA
mA
kΩ
kΩ
kΩ
%
ms
23.25
26
11
11
±3.5
1
Invalid Signature Resistance During Mark Event (Notes 6, 7)
10mA < I
CLASS
< 40mA, 12.5V < V
PORTP
< 21V
(Notes 8, 9)
V
PORTP
Pin Step to 17.5V, R
CLASS
= 30.9, I
CLASS
Within
3.5% of Ideal Value (Notes 8, 9)
V
PORTP
= 54V, V
NEG
= 3V
Tested at 600mA into V
NEG
, V
PORTP
= 54V
V
PORTP
= SHDN = V
NEG
= 57V
l
l
l
60
100
0.7
180
1.0
1
mA
Ω
μA
V
3
0.45
100
0.15
1
0.4
12
16.5
1
V
kΩ
V
μA
V
V
μA
42691fc
3
LTC4269-1
ELECTRICAL CHARACTERISTICS
PARAMETER
PWM Controller (Note 10)
Power Supply
V
CC
Turn-On Voltage, V
CC(ON)
V
CC
Turn-Off Voltage, V
CC(OFF)
V
CC
Hysteresis
V
CC
Shunt Clamp
V
CC
Supply Current (I
CC
)
V
CC
Start-Up Current
Feedback Amplifier
Feedback Regulation Voltage (V
FB
)
Feedback Pin Input Bias Current
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
Reference Voltage Line Regulation
Feedback Amplifier Voltage Gain
Soft-Start Charging Current
Soft-Start Discharge Current
Control Pin Threshold (V
CMP
)
Gate Outputs
PG, SG Output High Level
PG, SG Output Low Level
PG, SG Output Shutdown Strength
PG Rise Time
SG Rise Time
PG, SG Fall Time
Current Amplifier
Switch Current Limit at Maximum V
CMP
ΔV
SENSE
/ΔV
CMP
Sense Voltage Overcurrent Fault Voltage
Timing
Switching Frequency (f
OSC
)
Oscillator Capacitor Value (C
OSC
)
Minimum Switch On Time (t
ON(MIN)
)
Flyback Enable Delay Time (t
ENDLY
)
PG Turn-On Delay Time (t
PGDLY
)
Maximum Switch Duty Cycle
SYNC Pin Threshold
SYNC Pin Input Resistance
●
●
●
●
●
l
●
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
CONDITIONS
MIN
TYP
MAX
UNITS
14
8
4
19.5
4
15.3
9.7
5.6
20.5
6.4
180
16
11
6.5
10
400
1.251
1400
90
V
V
V
V
mA
μA
V
nA
μmho
μA
V
V
V
CC(ON)
– V
CC(OFF)
V
UVLO
= 0V, I
VCC
= 15mA
V
CMP
= Open (Note 11)
V
CC
= 10V
●
●
●
●
1.220
700
25
1.237
200
1000
55
2.56
0.84
R
CMP
Open
ΔI
C
= ±10μA
V
FB
= 0.9V
V
FB
= 1.4V
12V ≤ V
CC
≤ 18V
V
CMP
= 1.2V to 1.7V
V
SFST
= 1.5V
V
SFST
= 1.5V, V
UVLO
= 0V
Duty Cycle = Min
6.6
16
0.8
●
●
●
0.005
1400
20
1.3
1
7.4
0.01
1.6
11
15
10
0.02
25
%/ V
V/ V
μA
mA
V
8
0.05
2.3
V
V
V
ns
ns
ns
V
UVLO
= 0V; I
PG
, I
SG
= 20mA
C
PG
= 1nF
C
SG
= 1nF
C
PG
, C
SG
= 1nF
V
SENSE+
V
SENSE+
, V
SFST
< 1V
C
OSC
= 100pF
(Note 12)
●
●
88
98
0.07
206
110
230
110
200
mV
V/ V
mV
kHz
pF
ns
ns
ns
%
●
●
84
33
100
200
265
200
85
88
1.53
40
2.1
V
kΩ
42691fc
4
LTC4269-1
ELECTRICAL CHARACTERISTICS
PARAMETER
Load Compensation
Load Compensation to V
SENSE
Offset Voltage
Feedback Pin Load Compensation Current
UVLO Function
UVLO Pin Threshold (V
UVLO
)
UVLO Pin Bias Current
V
UVLO
= 1.2V
V
UVLO
= 1.3V
●
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
CONDITIONS
V
RCMP
with V
SENSE+
= 0V
V
SENSE+
= 20mV, V
FB
= 1.230V
1.215
–0.25
–4.50
MIN
TYP
1
20
1.240
0
–3.4
1.265
0.25
–2.50
MAX
UNITS
mV
μA
V
μA
μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3:
Active high PWRGD internal clamp self-regulates to 14V with
respect to V
NEG
. V
CC
has internal 19.5V clamp with respect to GND.
Note 4:
All voltages are with respect to V
PORTN
pin unless otherwise noted.
Note 5:
Input voltage specifications are defined with respect to LTC4269-1
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 6:
Signature resistance is measured via the ΔV/ΔI method with the
minimum ΔV of 1V. The LTC4269-1 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 7:
An invalid signature after the 1st classification event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8:
Class accuracy is with respect to the ideal current defined as
1.237/R
CLASS
and does not include variations in R
CLASS
resistance.
Note 9:
This parameter is assured by design and wafer level testing.
Note 10:
V
CC
= 14V; PG, SG Open; V
CMP
= 1.5V, V
SENSE–
= 0V, R
CMP
= 1k,
R
tON
= 90k, R
PGDLY
= 27.4k, R
ENDLY
= 90k, unless otherwise specified. All
voltages are with respect to GND.
Note 11:
Supply current does not include gate charge current to the
MOSFETs. See the Applications Information section.
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