SP8852E
2·7GHz Parallel Load Professional Synthesiser
Preliminary Information
Supersedes January 1996 version, DS4237 - 1.2
DS4237 - 2.0 June 1998
The SP8852E is one of a family of parallel load synthesisers
containing all the elements apart from the loop amplifier to
fabricate a PLL synthesis loop. Other parts in the series are
the SP8854E which has hard wired reference counter pro-
gramming and requires only a single 16-bit programming
word, and the SP8855E which is fully programmable using
hard wired links or switches.
The SP8852E is programmed using a 16-bit parallel data
bus. Data can be stored in one of two internal buffers, selected
by a single address bit on the input interface. In order to fully
program the device, two 16-bit words are required, one to
select the RF division ratio (A and M counters) and phase
detector gain, and one to set the 10-bit reference divider
count, phase detector state and sense. Once the reference
divide ratio has been set, frequency changes can be made by
a single 16-bit data load entry to the RF divider chain.
B4
B3
B2
B1
B0
0V (PRESCALER)
RF INPUT
RF INPUT
V
CC
(PRESCALER)
VEE
LOCK DETECT
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
1 44
SP8852E
STROBE
ADDRESS
NC
NC
NC
NC
NC
NC
NC
NC
NC
FEATURES
s
2·7 GHz Operating Frequency
s
Single 5V Supply
s
Low Power Consumption <1·3W
s
High Comparison Frequency : 20MHz
s
High Gain Phase Detector : 1mA/rad
s
Zero ‘Dead Band’ Phase Detector
s
Wide Range of RF and Reference Division Ratios
s
Programming by Dual Word Data Transfer
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Operating temperature
Storage temperature
Prescaler and reference input voltage
Data inputs
Junction temperature
20·3V
to
16V
255°C
to1100°C
265°C
to
1150°C
2·5Vp-p
V
CC
10·3V
V
EE
20·3V
1175°C
C-LOCK DETECT
R
SET
CHARGE PUMP OUTPUT
CHARGE PUMP REF
NC
NC
F
PD
*
F
REF
*
V
CC
REF OSC CAPACITOR
REF IN/CRYSTAL
HC44
*F
PD
and F
REF
outputs are reversed by the phase
detector sense bit in the F1/F2 programming word, bit
12. The above diagram is correct when bit 12 is high.
Fig. 1 Pin connections - top view
THERMAL DATA
u
JC
= 5°C/W
u
JA
= 53°C/W
ESD PROTECTION
1000V, human body model
ORDERING INFORMATION
SP8852E KG HCAR
Non-standard temperature range,
255°C
to
1100°C,
standard product screening
SP8852E IG HCAR
Industrial temperature range,
240°C
to
185°C,
standard product screening
SP8852E
V
CC
PRESCALER
RF INPUT
RF INPUT
0V
15
13
14
14
MODULUS
CONTROL
F
PD
48/9
3-BIT
A COUNTER
11-BIT
M COUNTER
PRESCALER
B0
STROBE
ADDRESS
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
39
38
11
10
9
8
7
6
5
4
3
2
1
44
43
42
41
40
B2
B3
B13 B14
B15
LOAD
RF BUFFER
20
21
17
CHARGE PUMP OUTPUT
CHARGE PUMP REFERENCE
LOCK DETECT OUTPUT
R
SET
C-LOCK DETECT
F
PD
*
F
REF
*
PHASE
DETECTOR
19
18
24
25
LOAD
INPUT
INTERFACE
REFERENCE BUFFER
B0
B9
B10
B12
10-BIT REFERENCE
DIVIDER
F
REF
*FREF and FPD outputs are reversed
by the phase detector sense bit, bit 12
in the programming word. The pin
allocations shown are correct when
bit 12 is high.
28
27
26
16
V
CC
V
EE
REFERENCE
CRYSTAL
REFERENCE
CAPACITOR
Fig. 2 Block diagram
2
SP8852E
Pin
1-11, 40-44
Description
These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for
the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers
for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on
these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high
and frozen in buffers when pin 39 is low.
Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into
pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC
biased.
A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give
an external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time constant and can
be used to vary the sensitivity of the phase lock indicator.
An external resistor from pin 19 to V
CC
sets the charge pump output current.
The phase detector output is a single ended charge pump sourcing or sinking current to the
inverting input of an external loop filter. The direction is controlled by bit 12 of the reference word.
For bit 12 = 1 and F
PD
or RF phase leads Ref phase pin 20 will sink current (see Table 3).
Connected to the non-inverting input of the loop filter to set the optimum DC bias.
Not Connected.
Not connected.
F
PD
if pin 23 is high
F
REF
if pin 23 is low
F
PD
if pin 23 is low
F
REF
if pin 23 is high
RF divider output pulses. F
PD
= RF input frequency/(M.N1A). Pulse width = 8 RF input cycles
(1 cycle of the divide by 8 prescaler output).
Reference divider output pulses. F
REF
= reference input frequency/R. Pulse width = high period
of Ref input.
Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as
an onboard crystal oscillator.
This pin is the input buffer amplifier for an external reference signal. This amplifier provides the
active element if an onboard crystal oscillator is used.
Not connected.
Controls which buffer the data on the input bus goes to. Pin 38 high sends data to the RF divider
group of functions. Pin 38 low sends data to the Ref divider group of functions (see Fig. 6). Open
circuit = high.
When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump
output is disabled. The data on the input bus is loaded into the buffers selected by the ADDRESS
input state (pin 38) when pin 39 goes low. When pin 39 is low the data is fixed in the buffers, the
buffers are loaded into the counter and control register, all the counters are active, and the
charge pump is enabled. Open circuit = high.
13 (RF INPUT)
14 (RF INPUT)
17 (LOCK DETECT INPUT)
18 (C-LOCK DETECT)
19 (R
SET
)
20 (CHARGE PUMP OUTPUT)
21 (CHARGE PUMP REF)
22
23
24
25
27 (Ref. oscillator capacitor)
28 (REF IN/XTAL)
29-37
38 (ADDRESS)
39 (STROBE)
Table 1 Pin descriptions
3
SP8852E
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions unless otherwise stated
T
AMB
=
2
55°C to
1100°C
(KG parts),
2
40°C to
185°C
(IG parts); V
CC
= 4·75V to 5·25V
Value
Characteristic
Pin
Min.
Typ.
180
25
56
1
Max.
240
17
16383
1023
50
10
0
16
20·8
21·4
300
61·4
61·5
500
61·7
100
110
MHz
MHz
dBm
V
V
mV
mA
WRT V
CC
, 2·2kΩ to 0V
WRT V
CC
, 2·2kΩ to 0V
I
OUT
= 3mA
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 1
62·0
62·3
62·5
mA
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 1·5
63·4
63·8
64·1
mA
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 2·5
65·4
66·1
66·5
mA
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 4·0
Input bus logic level high
Input bus logic level low
Input bus current source
Input bus current sink
Up/down current matching
CHARGE PUMP REFERENCE voltage
1-11, 38-44
1-11, 38-44
1-11, 38-44
2200
1-11, 38-44
20
21
10
65
V
CC
20·5
V
CC
21·6
19
19
18
50
100
0·5
1·6
110
2
3·5
1
V
V
µA
µA
%
V
V
IN
= 0V
V
IN
= V
CC
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA
I
PIN19
= 1·6mA, current
multiplication factor = 1·0
V
I
PIN19
= 1·6mA, current
multiplication factor = 4·0
R
SET
current
R
SET
voltage
C-LOCK DETECT current
STROBE pulse width
Data setup time
mA
V
µA
ns
ns
Note 2
I
PIN19
= 1·6mA
V
PIN18
= 4·7V
Note 3
Note 3
Ref division ratio >2. See note 1
Units
Conditions
Supply current
RF input sensitivity
RF division ratio
Reference division ratio
Comparison frequency
Reference input frequency
Reference input voltage
F
REF
/F
PD
output voltage high
F
REF
/F
PD
output voltage low
LOCK DETECT output voltage
CHARGE PUMP current
18, 26
13,14
13,14, 24
28, 25
28, 24, 25
28
28
24, 25
24, 25
17
19, 20, 21
mA
dBm
100MHz to 2·7GHz. See note 3.
NOTES
1. Lower frequencies may be used provided that slew rates are maintained.
2. Pin 19 current3multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.
3. Guranteed but not tested.
4
SP8852E
120
TYPICAL OVERLOAD
RF INPUT TO PIN 13 (dBm)
110
17
0
25
210
GUARANTEED
OPERATING WINDOW
220
TYPICAL SENSITIVITY
230
100MHz
1GHz
2GHz 2·7GHz
10GHz
FREQUENCY
Fig. 3 Input sensitivity
j1
j
0.5
j2
Z
O
= 50Ω
j
0.2
j5
0
1·1GHz
0.2
0.5
1
2
5
50MHz
2·5GHz
2
j
5
2
j
0.2
2
j
0.5
2
j
1
2
j
2
Fig. 4 RF input impedance
5
京公网安备 11010802033920号
EEWORLD
