SP8852EKGHCAR datasheet, PDF - EEWORLD Datasheet

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SP8852EKGHCAR: DescriptionPLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC44; Categoryaccessories; File Size132KB，13 Pages; ManufacturerMitel; Websitehttps://www.mitel.com

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SP8852EKGHCAR Overview

PLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC44

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SP8852E

2·7GHz Parallel Load Professional Synthesiser

Preliminary Information

Supersedes January 1996 version, DS4237 - 1.2

DS4237 - 2.0 June 1998

The SP8852E is one of a family of parallel load synthesisers

containing all the elements apart from the loop amplifier to

fabricate a PLL synthesis loop. Other parts in the series are

the SP8854E which has hard wired reference counter pro-

gramming and requires only a single 16-bit programming

word, and the SP8855E which is fully programmable using

hard wired links or switches.

The SP8852E is programmed using a 16-bit parallel data

bus. Data can be stored in one of two internal buffers, selected

by a single address bit on the input interface. In order to fully

program the device, two 16-bit words are required, one to

select the RF division ratio (A and M counters) and phase

detector gain, and one to set the 10-bit reference divider

count, phase detector state and sense. Once the reference

divide ratio has been set, frequency changes can be made by

a single 16-bit data load entry to the RF divider chain.

0V (PRESCALER)

RF INPUT

(PRESCALER)

VEE

LOCK DETECT

B10

B11

B12

B13

B14

B15

1 44

SP8852E

STROBE

ADDRESS

FEATURES

2·7 GHz Operating Frequency

Single 5V Supply

Low Power Consumption <1·3W

High Comparison Frequency : 20MHz

High Gain Phase Detector : 1mA/rad

Zero ‘Dead Band’ Phase Detector

Wide Range of RF and Reference Division Ratios

Programming by Dual Word Data Transfer

ABSOLUTE MAXIMUM RATINGS

Supply voltage

Operating temperature

Storage temperature

Prescaler and reference input voltage

Data inputs

Junction temperature

20·3V

16V

255°C

to1100°C

265°C

1150°C

2·5Vp-p

10·3V

20·3V

1175°C

C-LOCK DETECT

SET

CHARGE PUMP OUTPUT

CHARGE PUMP REF

REF

REF OSC CAPACITOR

REF IN/CRYSTAL

HC44

and F

REF

outputs are reversed by the phase

detector sense bit in the F1/F2 programming word, bit

12. The above diagram is correct when bit 12 is high.

Fig. 1 Pin connections - top view

THERMAL DATA

= 5°C/W

= 53°C/W

ESD PROTECTION

1000V, human body model

ORDERING INFORMATION

SP8852E KG HCAR

Non-standard temperature range,

255°C

1100°C,

standard product screening

SP8852E IG HCAR

Industrial temperature range,

240°C

185°C,

standard product screening

SP8852E

1-11, 40-44

Description

These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for

the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers

for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on

these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high

and frozen in buffers when pin 39 is low.

Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into

pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC

biased.

A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give

an external indication of phase lock.

A capacitor connected to this point determines the lock detect integrator time constant and can

be used to vary the sensitivity of the phase lock indicator.

An external resistor from pin 19 to V

sets the charge pump output current.

The phase detector output is a single ended charge pump sourcing or sinking current to the

inverting input of an external loop filter. The direction is controlled by bit 12 of the reference word.

For bit 12 = 1 and F

or RF phase leads Ref phase pin 20 will sink current (see Table 3).

Connected to the non-inverting input of the loop filter to set the optimum DC bias.

Not Connected.

Not connected.

if pin 23 is high

REF

if pin 23 is low

REF

if pin 23 is high

RF divider output pulses. F

= RF input frequency/(M.N1A). Pulse width = 8 RF input cycles

(1 cycle of the divide by 8 prescaler output).

Reference divider output pulses. F

REF

= reference input frequency/R. Pulse width = high period

of Ref input.

Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as

an onboard crystal oscillator.

This pin is the input buffer amplifier for an external reference signal. This amplifier provides the

active element if an onboard crystal oscillator is used.

Not connected.

Controls which buffer the data on the input bus goes to. Pin 38 high sends data to the RF divider

group of functions. Pin 38 low sends data to the Ref divider group of functions (see Fig. 6). Open

circuit = high.

When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump

output is disabled. The data on the input bus is loaded into the buffers selected by the ADDRESS

input state (pin 38) when pin 39 goes low. When pin 39 is low the data is fixed in the buffers, the

buffers are loaded into the counter and control register, all the counters are active, and the

charge pump is enabled. Open circuit = high.

13 (RF INPUT)

14 (RF INPUT)

17 (LOCK DETECT INPUT)

18 (C-LOCK DETECT)

19 (R

SET

)

20 (CHARGE PUMP OUTPUT)

21 (CHARGE PUMP REF)

27 (Ref. oscillator capacitor)

28 (REF IN/XTAL)

29-37

38 (ADDRESS)

39 (STROBE)

Table 1 Pin descriptions

SP8852EKGHCAR Related Products

	SP8852EKGHCAR	SP8852	SP8852EIGHCAR	SP8852E
Description	PLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC44	PLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC44	PLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC44	PLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC44

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