LTC6954IUFF-2#TRPBF datasheet, PDF

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LTC6954IUFF-2#TRPBF: DescriptionClock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP T/R; File Size2MB，56 Pages; ManufacturerADI; Websitehttps://www.analog.com

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LTC6954IUFF-2#TRPBF Overview

Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP T/R

LTC6954IUFF-2#TRPBF Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Type	Fanout Buffer
Fanout	1:3
Number of Outputs per Chip	3
Maximum Input Frequency (MHz)	1400
Maximum Propagation Delay Time @ Maximum CL (ns)	0.625@3.15V to 3.45V
Absolute Propagation Delay Time (ns)	0.625
Maximum Duty Cycle	55%
Output Logic Level	CMOS\|LVDS\|LVPECL
Minimum Operating Supply Voltage (V)	3.15
Typical Operating Supply Voltage (V)	3.3
Maximum Operating Supply Voltage (V)	3.45
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	105
Supplier Temperature Grade	Industrial
Packaging	Tape and Reel
Supplier Package	QFN EP
Pin Count	36
Standard Package Name	QFN
Mounting	Surface Mount
Package Height	0.75(Max)
Package Length	7
Package Width	4
PCB changed	36
Lead Shape	No Lead

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LTC6954

Low Phase Noise,

Triple Output Clock

Distribution Divider/Driver

FEATURES

DESCRIPTION

The

LTC

6954

is a family of very low phase noise clock

distribution parts. Each part has three outputs and each

output has an individually programmable frequency

divider and delay. There are four members of the family,

differing in their output logic signal type:

LTC6954-1:

Three LVPECL outputs

LTC6954-2:

Two LVPECL and one LVDS/CMOS outputs

LTC6954-3:

One LVPECL and two LVDS/CMOS outputs

LTC6954-4:

Three LVDS/CMOS outputs

Each output is individually programmable to divide the

input frequency by any integer from 1 to 63, and to delay

each output by 0 to 63 input clock cycles. The output duty

cycle is always 50%, regardless of the divide number.

The LVDS/CMOS outputs are jumper selectable via the

OUTxSEL pins to provide either an LVDS logic output or

a CMOS logic output.

The LTC6954 also features Linear Technology’s EZSync

system for perfect clock synchronization and alignment

every time.

All device settings are controlled through an SPI-compatible

serial port.

Low Noise Clock Distribution: Suitable for High

Speed/High Resolution ADC Clocking

Additive Jitter < 20fs

RMS

(12kHz to 20MHz)

Additive Jitter < 85fs

RMS

(10Hz to Nyquist)

1.8GHz Maximum Input Frequency

(LTC6954-1 When DELAY = 0)

1.4GHz Maximum Input Frequency

(LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4)

EZSync™ Clock Synchronization Compatible

Three Independent, Low Noise Outputs

Four Output Combinations Available

Three Independent Programmable Dividers Covering

All Integers from 1 to 63

Three Independent Programmable Delays Covering

All Integers from 0 to 63

–40°C to 105°C Junction Temperature Range

APPLICATIONS

Clocking High Speed, High Resolution ADCs, DACs

and Data Acquisition Systems

Low Jitter Clock Distribution

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 8319551, 8819472.

TYPICAL APPLICATION

0.1µF

UP TO 1.4GHz

49.9

SYNC

OUT0SEL

3.3V

OUT1SEL

OUT2SEL

SDO

SPI

SERIAL

PORT

SDI

SCLK

GND

SERIAL

PORT

AND

DIGITAL

SYNC

CONTROL

–

49.9

DELAY

0 TO 63

DELAY

0 TO 63

DELAY

0 TO 63

DIVIDE

1 TO 63

DIVIDE

1 TO 63

DIVIDE

1 TO 63

LTC6954-3

LVPECL OUTPUT

FREQUENCY

UP TO 1.8GHz

LVDS OUTPUT

FREQUENCY

UP TO 1.4GHz

CMOS OUTPUT

FREQUENCY

UP TO 250MHz

3.3V

Additive Phase Noise vs Offset Frequency,

= 622.08MHz, Mx[5:0] = 4,

OUTx

= 155.52MHz

–120

ADDITIVE PHASE NOISE (dBc/Hz)

–130

–140

–150

–160

–170

–180

6954 TA01a

OUT0

–

OUT1

–

OUT2

–

100

10k 100k

OFFSET FREQUENCY (Hz)

10M

6954 TA01b

Rev. A

Document Feedback

For more information

www.analog.com

LTC6954IUFF-2#TRPBF Related Products

	LTC6954IUFF-2#TRPBF	LTC6954IUFF-1#PBF	LTC6954IUFF-1#TRPBF	LTC6954IUFF-2#PBF	LTC6954IUFF-3#PBF	LTC6954IUFF-3#TRPBF	LTC6954IUFF-4#PBF	LTC6954IUFF-4#TRPBF
Description	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP T/R	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP Tube	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP T/R	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP Tube	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP Tube	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP T/R	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP Tube	Clock Fanout Buffer 3-OUT 1-IN 1:3 36-Pin QFN EP T/R
EU restricts the use of certain hazardous substances	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant
ECCN (US)	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Part Status	Active	Active	Active	Active	Active	Active	Active	Active
HTS	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01
Type	Fanout Buffer	Fanout Buffer	Fanout Buffer	Fanout Buffer	Fanout Buffer	Fanout Buffer	Fanout Buffer	Fanout Buffer
Fanout	1:3	1:3	1:3	1:3	1:3	1:3	1:3	1:3
Number of Outputs per Chip	3	3	3	3	3	3	3	3
Maximum Input Frequency (MHz)	1400	1800	1800	1400	1400	1400	1400	1400
Maximum Propagation Delay Time @ Maximum CL (ns)	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V	0.625@3.15V to 3.45V
Absolute Propagation Delay Time (ns)	0.625	0.625	0.625	0.625	0.625	0.625	0.625	0.625
Maximum Duty Cycle	55%	55%	55%	55%	55%	55%	55%	55%
Output Logic Level	CMOS\|LVDS\|LVPECL	LVPECL	LVPECL	LVPECL\|LVDS\|CMOS	CMOS\|LVDS\|LVPECL	CMOS\|LVDS\|LVPECL	LVDS\|CMOS	CMOS\|LVDS
Minimum Operating Supply Voltage (V)	3.15	3.15	3.15	3.15	3.15	3.15	3.15	3.15
Typical Operating Supply Voltage (V)	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3
Maximum Operating Supply Voltage (V)	3.45	3.45	3.45	3.45	3.45	3.45	3.45	3.45
Minimum Operating Temperature (°C)	-40	-40	-40	-40	-40	-40	-40	-40
Maximum Operating Temperature (°C)	105	105	105	105	105	105	105	105
Supplier Temperature Grade	Industrial	Industrial	Industrial	Industrial	Industrial	Industrial	Industrial	Industrial
Packaging	Tape and Reel	Tube	Tape and Reel	Tube	Tube	Tape and Reel	Tube	Tape and Reel
Supplier Package	QFN EP	QFN EP	QFN EP	QFN EP	QFN EP	QFN EP	QFN EP	QFN EP
Pin Count	36	36	36	36	36	36	36	36
Standard Package Name	QFN	QFN	QFN	QFN	QFN	QFN	QFN	QFN
Mounting	Surface Mount	Surface Mount	Surface Mount	Surface Mount	Surface Mount	Surface Mount	Surface Mount	Surface Mount
Package Height	0.75(Max)	0.75(Max)	0.75(Max)	0.75(Max)	0.75(Max)	0.75(Max)	0.75(Max)	0.75(Max)
Package Length	7	7	7	7	7	7	7	7
Package Width	4	4	4	4	4	4	4	4
PCB changed	36	36	36	36	36	36	36	36
Lead Shape	No Lead	No Lead	No Lead	No Lead	No Lead	No Lead	No Lead	No Lead

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