PCF2123
SPI Real time clock/calendar
Rev. 5 — 27 April 2011
Product data sheet
1. General description
The PCF2123 is a CMOS
1
Real-Time Clock (RTC) and calendar optimized for low power
applications. Data is transferred serially via a Serial Peripheral Interface (SPI-bus) with a
maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing
the possibility to generate a wake-up signal on an interrupt pin. An offset register allows
fine tuning of the clock.
2. Features and benefits
Real time clock provides year, month, day, weekday, hours, minutes, and seconds
based on a 32.768 kHz quartz crystal
Low backup current while running: typical 100 nA at V
DD
= 2.0 V and T
amb
= 25
°C
Resolution: seconds to years
Watchdog functionality
Freely programmable timer and alarm with interrupt capability
Clock operating voltage: 1.1 V to 5.5 V
3 line SPI-bus with separate, but combinable data input and output
Serial interface at V
DD
= 1.6 V to 5.5 V
1 second or 1 minute interrupt output
Integrated oscillator load capacitors for C
L
= 7 pF
Internal Power-On Reset (POR)
Open-drain interrupt and clock output pins
Programmable offset register for frequency adjustment
3. Applications
Time keeping application
Battery powered devices
Metering
High duration timers
Daily alarms
Low standby power applications
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in
Section 21.
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
4. Ordering information
Table 1.
Ordering information
Package
Name
PCF2123BS/1
PCF2123TS/1
PCF2123U/5GA/1
PCF2123U/10AA/1
PCF2123U/12AA/1
PCF2123U/12HA/1
[1]
[2]
[3]
Unsawn wafer.
Sawn 6 inch wafer on Film Frame Carrier (FFC) for 6 inch wafer, see
Figure 37 on page 53.
Sawn 6 inch wafer with gold bumps on Film Frame Carrier (FFC) for 8 inch wafer, see
Figure 38 on page 53.
Type number
Description
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
×
3
×
0.85 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
12 bonding pads
[1]
12 bonding pads
[2]
wafer level chip size package; 12 bumps
[3]
wafer level chip size package; 12 bumps
[3]
Version
SOT758-1
SOT402-1
PCF2123U/10
PCF2123U/10
PCF2123U/12
PCF2123U/12
HVQFN16
TSSOP14
wire bond die
wire bond die
WLCSP12
WLCSP12
5. Marking
Table 2.
Marking codes
Marking code
123
PCF2123
PC2123-1
PC2123-1
PC2123-1
PC2123-1
Type number
PCF2123BS/1
PCF2123TS/1
PCF2123U/5GA/1
PCF2123U/10AA/1
PCF2123U/12AA/1
PCF2123U/12HA/1
PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
2 of 63
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
6. Block diagram
OSCI
C
OSCI
OSCO
C
OSCO
MONITOR
0Dh
OFFSET FUNCTION
Offset_register
TIMER FUNCTION
0Eh
0Fh
Timer_clkout
Countdown_timer
CONTROL
00h
POWER ON
RESET
01h
Control_1
Control_2
TIME
02h
WATCH
DOG
03h
04h
05h
06h
SDO
SDI
SCL
CE
R
pd
SPI
INTERFACE
07h
08h
Seconds
Minutes
Hours
Days
Weekdays
Months
Years
ALARM FUNCTION
09h
0Ah
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
013aaa223
CLKOE
OSCILLATOR
32.768 kHz
DIVIDER
CLOCK OUT
CLKOUT
TEST
V
DD
V
SS
INTERRUPT
INT
PCF2123
0Bh
0Ch
Fig 1.
Block diagram of PCF2123
PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
3 of 63
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
7. Pinning information
7.1 Pinning
16 OSCI
13 V
DD
12 CLKOUT
11 CLKOE
15 n.c.
terminal 1
index area
OSCO
TEST
INT
CE
1
2
14 n.c.
PCF2123BS
3
4
5
6
7
8
10 SCL
9
SDI
OSCI
OSCO
n.c.
TEST
INT
CE
1
2
3
4
5
6
7
001aai551
14 V
DD
13 CLKOUT
12 CLKOE
PCF2123TS
11 n.c.
10 SCL
9
8
SDI
SDO
n.c.
V
SS
n.c.
SDO
001aai550
V
SS
Transparent top view
For mechanical details, see
Figure 30 on page 45.
Top view. For mechanical details, see
Figure 31 on
page 46.
Fig 2.
Pin configuration for HVQFN16 (PCF2123BS/1)
Fig 3.
Pin configuration for TSSOP14 (PCF2123TS/1)
6
OSCI
7
5
OSCO
8
4
TEST
INT
CE
V
SS
9
10
11
12
2
V
DD
CLKOUT
CLKOE
PCF2123U
3
SCL
SDI
1
SDO
001aai544
Viewed from active side. For mechanical details, see
Figure 33 on page 48
and
Figure 34 on
page 49.
Fig 4.
Pin configuration for PCF2123Ux (bare die)
PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
4 of 63
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
HVQFN16
TSSOP14
PCF2123Ux
(PCF2123BS/1) (PCF2123TS/1) (bare die)
OSCI
OSCO
n.c.
TEST
INT
CE
V
SS
SDO
SDI
SCL
CLKOE
V
DD
16
1
6, 7, 14, 15
2
3
4
5
[1]
8
9
10
11
13
1
2
3, 11
4
5
6
7
8
9
10
12
13
14
7
8
-
9
10
11
12
[2]
1
2
3
4
5
6
oscillator input; high-impedance node; minimize wire length
between quartz and package
oscillator output; high-impedance node; minimize wire length
between quartz and package
do not connect and do not use as feed through; connect to
V
DD
if floating pins are not allowed
test pin; not user accessible; connect to V
SS
or leave floating
(internally pulled down)
interrupt output (open-drain; active LOW)
chip enable input (active HIGH) with internal pull down
ground
serial data output, push-pull; high-impedance when not
driving; can be connected to SDI for single wire data line
serial data input; may float when CE is inactive
serial clock input; may float when CE is inactive
CLKOUT enable or disable pin; enable is active HIGH
clock output (open-drain)
supply voltage; positive or negative steps in V
DD
may affect
oscillator performance; recommend 100 nF decoupling close
to the device (see
Figure 29)
Description
CLKOUT 12
[1]
[2]
The die paddle (exposed pad) is wired to V
SS
and should be electrically isolated.
The substrate (rear side of the die) is wired to V
SS
and should be electrically isolated.
PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
5 of 63
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