PIC24FJ256GA110 FAMILY
PIC24FJ256GA110 Family
Silicon Errata and Data Sheet Clarification
The PIC24FJ256GA110 family devices that you have
received conform functionally to the current Device Data
Sheet (DS39905E), except for the anomalies described
in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC24FJ256GA110 family
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon
revision (A6).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
Using the appropriate interface, connect the
device
to
the
MPLAB
ICD
2
programmer/debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device,
and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select
Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number
and
Device
Revision ID value appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
2.
3.
4.
Data Sheet clarifications and corrections start on
page 12,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The
DEVREV
values
for
the
various
PIC24FJ256GA110 family silicon revisions are
shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device
ID
(1)
101Eh
1016h
100Eh
1006h
101Ah
1012h
01h
03h
04h
Revision ID for
Silicon Revision
(2)
A3
A5
A6
PIC24FJ128GA108
PIC24FJ64GA108
PIC24FJ256GA106
PIC24FJ192GA106
PIC24FJ128GA106
PIC24FJ64GA106
Part Number
Device
ID
(1)
100Ah
1002h
1018h
1010h
1008h
1000h
01h
03h
04h
Revision ID for
Silicon Revision
(2)
A3
A5
A6
Part Number
PIC24FJ256GA110
PIC24FJ192GA110
PIC24FJ128GA110
PIC24FJ64GA110
PIC24FJ256GA108
PIC24FJ192GA108
Note 1:
2:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the
“PIC24FJXXXGA0XX Flash Programming Specification”
(DS39768) for detailed information
on Device and Revision IDs for your specific device.
2008-2013 Microchip Technology Inc.
DS80368N-page 1
PIC24FJ256GA110 FAMILY
TABLE 2:
Module
Core
Core
JTAG
UART
I/O
SPI
CTMU
UART
UART
SPI
UART
UART
UART
Core
Memory
ICSP™
RTCC
I
2
C™
Module
I
2
C™
Module
A/D Converter
SPI
Core
SPI/PPS
Oscillator
CTMU
Output
Compare
Interrupts
A/D Converter
Note 1:
INTx
—
LPRC
A/D Trigger
—
SILICON ISSUE SUMMARY
Feature
RAM Operation
BOR
Device
Programming
—
PORTB
Master mode
—
UERIF Interrupt
FIFO Error Flags
Enhanced Buffer
modes
IrDA
®
IrDA
IrDA
Instruction Set
Program Space
Visibility
—
—
Master mode
Slave mode
—
Enhanced Buffer
mode
Code Protection
—
Item
Number
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
Issue Summary
RAM issues in Doze mode.
BOR issues in enabled on-chip regulator.
JTAG issues in device programming.
Framing errors in UART.
RB5 issues in open-drain operation.
Early one-half clock cycles.
CTMU issues as a trigger source.
UART error interrupt issue.
Error bits settings for receive FIFO.
Errors in enhanced buffer interrupts.
Issues in 8-bit mode using IrDA
®
endec.
Framing errors in 8-bit mode using IrDA
endec.
Transmission errors in 9-bit mode using IrDA
endec.
Read-After-Write stall conditions inside a
REPEAT
loop.
False error trap conditions when accessing
data in the PSV.
Inability of the ICSP/ICD port pair to read or
program.
Unexpected decrementing of the Alarm
Repeat Counter.
Acknowledgement issues in addressing slave
device.
Acknowledgement issues in Slave mode.
Debugging issues on 64-pin devices.
FIFO transfer issues in Enhanced Master
mode.
Applications unable to write when General
Segment Code Protection has been enabled.
ALTRP/ASCK1 functionality is not supported.
Issues with LPRC automatic restart following
BOR.
Issues in the CTMU in triggering automatic
A/D conversion.
Single missed compare events under certain
conditions.
External interrupts missed when writing to
INTCON2.
Module continues to draw current when
disabled.
Affected Revisions
(1)
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A5
X
A6
X
Only those issues indicated in the last column apply to the current silicon revision.
DS80368N-page 2
2008-2013 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
TABLE 2:
Module
CTMU
Oscillator
Output
Compare
UART
Oscillator
Note 1:
SILICON ISSUE SUMMARY (CONTINUED)
Feature
—
—
Interrupt
Transmit
Two-Speed
Start-up
Item
Number
29.
30.
31.
32.
33.
Issue Summary
Disabling module affects band gap.
POSCEN bit does not work with
Primary + PLL modes.
Interrupt flag may precede the output pin
change under certain circumstances.
A TX interrupt may occur before the data
transmission is complete.
This feature is not functional.
Affected Revisions
(1)
A3
X
X
X
X
X
A5
X
X
X
X
X
A6
X
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
2008-2013 Microchip Technology Inc.
DS80368N-page 3
PIC24FJ256GA110 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
3. Module: JTAG (Device Programming)
The JTAGEN Configuration bit can be pro-
grammed to ‘0’ while using the JTAG interface for
device programming. This may cause a situation
where JTAG programming can lock itself out of
being able to program the device.
Work around
None.
Affected Silicon Revisions
A3
X
A5
X
A6
X
1. Module: Core (RAM Operation)
If a RAM read is performed on the instruction
immediately prior to enabling Doze mode, an extra
read event may occur when Doze mode is
enabled. This has no effect on most SFRs and on
user RAM space. However, this could cause regis-
ters which also perform some action on a read
(such as auto-incrementing a pointer or removing
data from a FIFO buffer) to repeat that action,
possibly resulting in lost data or unexpected
operation.
Work around
Avoid reading registers which perform a second-
ary action (e.g., UART and SPI FIFO buffers, and
the RTCVAL registers) immediately prior to
entering Doze mode.
If this cannot be avoided, execute a
NOP
instruction before entering Doze mode.
Affected Silicon Revisions
A3
X
A5
X
A6
X
4
Module: UART
When the UART is operating using two Stop bits
(STSEL =
1),
it may sample the first Stop bit
instead of the second one. If the device being com-
municated with is one using one Stop bit in its
communications, this may lead to framing errors.
Work around
None.
Affected Silicon Revisions
A3
X
A5
A6
5. Module: I/O (PORTB)
When RB5 is configured as an open-drain output,
it remains in a high-impedance state. The settings
of LATB5 and TRISB5 have no effect on the pin’s
state.
Work around
If open-drain operation is not required, configure
RB5 as a regular I/O (ODCB<5> =
0).
If open-drain operation is required, there are two
options:
• select a different I/O pin for the open-drain
function; or
• place an external transistor on the pin, and
configure the pin as a regular I/O.
Affected Silicon Revisions
A3
X
A5
A6
2. Module: Core (BOR)
When the on-chip regulator is enabled (ENVREG
tied to V
DD
), a BOR event may spontaneously
occur under the following circumstances:
• V
DD
is less than 2.5V, and either:
• the internal band gap reference is being used as
a reference with the A/D Converter
(AD1PCFGH<1> or <0> =
0)
or comparators
(CMxCON<1:0> =
11);
or
• the CTMU module is enabled.
Work around
Limit the following activities to only those times
when the on-chip regulator is not in Tracking mode
(LVDIF (IFS4<8>) =
0):
• enabling the CTMU module;
• selecting the internal band gap as a reference
for the A/D Converter or the comparators.
Affected Silicon Revisions
A3
X
A5
A6
DS80368N-page 4
2008-2013 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
6. Module: SPIx (Master Mode)
In Master mode, both the SPIx Interrupt Flag
(SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled
(SPIBEN =
0);
and
• the module is configured for serial data output
changes on transition from clock active to clock
Idle state (CKE =
1)
If the application is using the interrupt flag to deter-
mine when data to be transmitted is written to the
transmit buffer, the data currently in the buffer may
be overwritten.
Work around
Before writing to the SPIx buffer, check the SCKx pin
to determine if the last clock edge has passed.
Example 1
(below) demonstrates a method for
doing this. In this example, pin RD1 functions as the
SPIx clock, SCKx, which is configured as Idle low.
Affected Silicon Revisions
A3
X
A5
A6
7. Module: CTMU
When the CTMU module is selected as the trigger
source (SYNCSEL<4:0> =
11000),
the input
capture and/or output compare trigger may not
work.
Work around
Manually trigger the input capture and/or output
compare module(s) after a CTMU event is
received. Be certain to compensate for any time
latency that results from manually triggering the
module.
Affected Silicon Revisions
A3
X
A5
A6
EXAMPLE 1:
CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCK
//wait for the transmission to complete
//wait for the last clock to finish
//write new data to the buffer
while(IFS0bits.SPI1IF == 0){}
while(PORTDbits.RD1 == 1){}
SPI1BUF = 0xFF;
2008-2013 Microchip Technology Inc.
DS80368N-page 5
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