PMK30EP
P-channel TrenchMOS extremely low level FET
Rev. 03 — 29 April 2010
Product data sheet
1. Product profile
1.1 General description
Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
1.3 Applications
Battery management
Load switching
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
25 °C
≤
T
j
≤
150 °C
T
sp
= 25 °C; V
GS
= -10 V;
see
Figure 1;
see
Figure 3
T
sp
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max Unit
-30
-14.
9
6.9
V
A
W
Static characteristics
R
DSon
V
GS
= -10 V; I
D
= -9.2 A;
T
j
= 25 °C; see
Figure 9
-
16
19
mΩ
Dynamic characteristics
Q
GD
gate-drain charge V
GS
= -10 V; I
D
= -9.2 A;
V
DS
= -15 V; T
j
= 25 °C;
see
Figure 11;
see
Figure 12
-
7
-
nC
NXP Semiconductors
PMK30EP
P-channel TrenchMOS extremely low level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S
S
S
G
D
D
D
D
source
source
source
gate
drain
drain
drain
drain
1
4
S
001aaa025
Simplified outline
8
5
Graphic symbol
D
G
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Package
Name
PMK30EP
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
PMK30EP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 29 April 2010
2 of 13
NXP Semiconductors
PMK30EP
P-channel TrenchMOS extremely low level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
sp
= 25 °C; V
GS
= -10 V;
see
Figure 1;
see
Figure 3
T
sp
= 100 °C; V
GS
= -10 V;
see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25 °C
T
sp
= 25 °C; t
p
≤
10 µs; pulsed
T
sp
= 25 °C; t
p
≤
10 µs; pulsed;
see
Figure 3
T
sp
= 25 °C; see
Figure 2
Conditions
25 °C
≤
T
j
≤
150 °C
25 °C
≤
T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
-30
-30
20
-14.9
-7.5
-28.8
6.9
150
150
-5.8
-23
Unit
V
V
V
A
A
A
W
°C
°C
A
A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
120
I
der
(%)
80
003aab618
120
P
der
(%)
80
003aab948
40
40
0
0
50
100
150
T
j
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of solder point temperature
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
PMK30EP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 29 April 2010
3 of 13
NXP Semiconductors
PMK30EP
P-channel TrenchMOS extremely low level FET
−10
2
Limit R
DSon
= V
DS
/I
D
I
D
(A)
−10
t
p
= 10
μs
003aab616
1 ms
10 ms
−1
DC
100 ms
−10
−1
−10
−1
−1
−10
V
DS
(V)
−10
2
T
sp
= 25 °C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
Conditions
see
Figure 4
Min
-
Typ
-
Max
18
Unit
K/W
10
2
Z
th(j
−
sp)
(K / W)
10
δ
= 0.5
0.2
0.1
1
0.05
0.02
P
003aab617
δ
=
t
p
T
10
−1
single pulse
t
p
t
T
10
−2
10
−4
10
−3
10
−2
10
−1
1
10
t
p
(s)
10
2
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
PMK30EP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 29 April 2010
4 of 13
NXP Semiconductors
PMK30EP
P-channel TrenchMOS extremely low level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= -250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= -250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= -250 µA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 7;
see
Figure 8
I
D
= -250 µA; V
DS
= V
GS
; T
j
= 150 °C;
see
Figure 7;
see
Figure 8
I
D
= -250 µA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 7;
see
Figure 8
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= -30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= -30 V; V
GS
= 0 V; T
j
= 70 °C
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; I
D
= -9.2 A; T
j
= 25 °C;
see
Figure 9
V
GS
= -10 V; I
D
= -9.2 A; T
j
= 150 °C;
see
Figure 9
V
GS
= -4.5 V; I
D
= -7.3 A; T
j
= 25 °C;
see
Figure 10;
see
Figure 9
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
total gate charge
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
I
S
= -3.45 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 14
V
DS
= -15 V; R
L
= 6
Ω;
V
GS
= -10 V;
R
G(ext)
= 6
Ω;
T
j
= 25 °C
I
D
= -9.2 A; V
DS
= -15 V; V
GS
= -10 V;
T
j
= 25 °C; see
Figure 11;
see
Figure 12
I
D
= -9.2 A; V
DS
= -15 V; V
GS
= -10 V;
see
Figure 11;
see
Figure 12
I
D
= -9.2 A; V
DS
= -15 V; V
GS
= -10 V;
T
j
= 25 °C; see
Figure 11;
see
Figure 12
I
D
= -9.2 A; V
DS
= -15 V; T
j
= 25 °C;
see
Figure 11;
see
Figure 12
V
DS
= -25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
50
7
7
-2.5
2240
325
220
10
8
56
21
-0.8
-
-
-
-
-
-
-
-
-
-
-
-1.2
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
V
Min
-30
-27
-1
-0.7
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
16
25
24
Max
-
-
-3
-
-3.3
-1
-10
-100
-100
19
31
30
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
PMK30EP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 29 April 2010
5 of 13
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