MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067 OVERVIEW
The S3067 transceiver implements SONET/SDH
and WDM serialization/deserialization, and transmis-
sion functions. The block diagram in Figure 4 shows
the basic operation of the chip. This chip can be
used to implement the front end of WDM equipment,
which consists primarily of the serial transmit inter-
face and the serial receive interface. The chip
handles all the functions of these two elements, in-
cluding parallel-to-serial and serial-to-parallel
conversion, clock generation, and system timing.
The system timing circuitry consists of management
of the data stream and clock distribution throughout
the front end.
S3067 has the ability to bypass the internal VCO
with an external source and also with the receive
clock. The device generates 14/15, 15/14, 16/17 and
17/16 clocks based upon the received clock and an
external clock to incorporate the FEC capability. The
dividers support the first two rates shown in Table 4.
The S3067 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
S3067
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. S3067 Supports six different code
rates, besides the normal rate, for each of the four
operating modes.
Suggested Interface Devices
AMCC
AMCC
S3076
S3062
OC-48 Clock Recovery Device
OC-48 Performance Monitor
Table 3. FEC Select
FEC 0
0
1
1
0
0
1
1
0
0
1
1
2
1
1
1
1
0
0
0
0
VCO
Divider
17
16
15
14
17
16
15
14
RSCLK
Divider
16
17
14
15
X
X
X
X
Table 2. Data Rate Select
RATESEL 0
0
0
1
1
RATESEL 1
0
1
0
1
Operating Mode
OC-3
OC-12
OC-24/GBE/FC
OC-48
0
1
0
1
0
1
Table 4. FEC Modes
Error Correcting Capability
8 bytes per 255-byte block
7 bytes per 255-byte block
6 bytes per 255-byte block
5 bytes per 255-byte block
4 bytes per 255-byte block
3 bytes per 255-byte block
Code Rate showing
Bandwidth Expansion due
to code words & FSB
255/238 = 7.14% increase
255/240 = 6.25% increase
255/242 = 5.37% increase
255/244 = 4.51% increase
255/246 = 3.66% increase
255/248 = 2.82% increase
Example of increased input clock
frequency for STS-48/STM-16 (MHz)
155.52*255/238 = 155.52 * 15/14 = 166.63
155.52*255/240 = 155.52 * 17/16 = 165.24
155.52*255/242 = 163.87
155.52*255/244 = 162.53
155.52*255/246 = 155.52 * 85/82 = 161.21
155.52*255/248 = 159.91
September 17, 2002/ Revision A
3
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 5. Clock Synthesizer
VCO
PD
LPF
VCOCLK
S3067
REFCLK
RSCLK
N
RSCLK Divider
FECSEL 2
FECSEL (0-1)
Where N = 14/15/16/17
M = 14/15/16/17
RSCLK
VCOCLK
=
N
M
M
VCO Divider
A high on FECSEL2 selects RSCLK divided by N. A
low on FECSEL2 selects the REFCLK. The REFCLK
or RSCLK divided by N is divided by 1/M (multiplied
by M) in the loop. The value of M and N can be
selected by FECSEL0 and FECSEL1.
When FECSEL2 = 0, VCOCLK = REFCLK * M. The
user must select the proper value of REFCLK and M
to get the desired VCOCLK frequency. When
FECSEL2 = 1, VCOCLK = (RSCLK * M)
÷
N. The
user must select the proper M/N ratio (with
FECSEL0 and FECSEL1) to get the desired
VCOCLK value. (See Tables 3 and 4.)
Example: OC-48 FEC capability of 8 bytes per
255-byte block. Required VCOCLK = 2.6656 GHz.
Method 1:
Required VCOCLK = 2.6656 GHz
FECSEL2 = 0, selects REFCLK
FECSEL0 = 1 and FECSEL1 = 0, selects VCO
divider(M) = 16
REFCLK = 2.6656 GHz
÷
16 = 166.60 MHz
VCOCLK = REFCLK
÷
(1/M) = 166.60 * 16 = 2.6656
GHz
Method 2:
Required VCOCLK = 2.6656 GHz
FECSEL2 = 1, selects RSCLK
FECSEL0 = 0 and FECSEL1 = 0, selects VCO
divider(M) = 17 and RSCLK divider(N) = 16
RSCLK = (2.6656 * 16)
÷
17 = 2.5088 GHz
VCOCLK = RSCLK
÷
N
÷
(1/M) = 2.5088 GHz
÷
16 *
17 = 2.6656 GHz.
September 17, 2002/ Revision A
5
Analogue and Mixed Signal
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