SPICE Device Model Si3909DV
Vishay Siliconix
Dual P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
•
P-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71511
S-50836
Rev.
B, 16-May-05
www.vishay.com
1
SPICE Device Model Si3909DV
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
V
GS(th)
I
D(on)
V
DS
= V
GS
, I
D
=
−
250
µA
V
DS
=
−5
V, V
GS
=
−4.5
V
V
GS
=
−4.5
V, I
D
=
−
1.8 A
Drain-Source On-State Resistance
a
Symbol
Test Condition
Simulated
Data
1.1
14
0.18
0.19
0.25
3.6
−0.78
Measured
Data
Unit
V
A
0.16
0.19
0.28
3.6
−0.83
S
V
Ω
r
DS(on)
V
GS
=
−3.6
V, I
D
=
−1.6
A
V
GS
=
−2.5
V, I
D
=
−1
A
Forward Transconductance
Diode Forward Voltage
a
a
g
fs
V
SD
V
DS
=
−10
V, I
D
=
−1.8
A
I
S
=
−1.05
A, V
GS
= 0 V
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
=
−1.05
A, di/dt = 100 A/µs
V
DD
=
−10
V, R
L
= 10
Ω
I
D
≅ −1
A, V
GEN
=
−4.5
V, R
G
= 6
Ω
V
DS
=
−10
V, V
GS
=
−4.5
V, I
D
=
−1.8
A
2.5
0.40
0.60
10
8
52
7
20
2.7
0.40
0.60
11
34
19
24
20
ns
nC
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 71511
S-50836
Rev.
B, 16-May-05
SPICE Device Model Si3909DV
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 71511
S-50836
Rev.
B, 16-May-05
www.vishay.com
3
Embedded System
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