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SI5410DU

Description
POWER, FET
Categorysemiconductor    Discrete semiconductor   
File Size145KB,9 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Download Datasheet Parametric View All

SI5410DU Overview

POWER, FET

SI5410DU Parametric

Parameter NameAttribute value
Lead-freeYes
EU RoHS regulationsYes
China RoHS regulationsYes
stateACTIVE
terminal coatingPURE MATTE TIN
Transistor typeGENERAL PURPOSE POWER
New Product
Si5410DU
Vishay Siliconix
N-Channel 40-V (D-S) MOSFET
PRODUCT SUMMARY
V
DS
(V)
40
R
DS(on)
(Ω)
0.018 at V
GS
= 10 V
0.021 at V
GS
= 4.5 V
I
D
(A)
a
12
12
Q
g
(Typ.)
10 nC
FEATURES
Halogen-free
• TrenchFET
®
Power MOSFET
• New Thermally Enhanced PowerPAK
®
ChipFET
®
Package
- Small Footprint Area
- Low On-Resistance
- Thin 0.8 mm Profile
• 100 % UIS Tested
D
Lot Traceability
and Date Code
Part # Code
RoHS
COMPLIANT
PowerPAK ChipFET Single
1
2
D
D
D
D
D
D
G
S
S
Marking Code
3
4
AJ
XXX
APPLICATIONS
• Load Switch, PA Switch, and Battery
Switch for Portable Applications
• DC-DC Synchronous Rectification
G
8
7
6
5
Bottom View
Ordering Information:
Si5410DU-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
T
C
= 25 °C
Continuous Drain Current (T
J
= 150 °C)
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
T
C
= 25 °C
T
A
= 25 °C
L = 0.1 mH
T
C
= 25 °C
Maximum Power Dissipation
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
d, e
T
J
, T
stg
P
D
I
DM
I
S
I
AS
E
AS
I
D
Symbol
V
DS
V
GS
Limit
40
± 20
12
a
12
a
9.8
b, c
7.9
b, c
30
12
a
2.6
b, c
19
18
31
20
3.1
b, c
2
b, c
- 55 to 150
260
W
mJ
A
Unit
V
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
b, f
Maximum Junction-to-Case (Drain)
t
5s
Steady State
Symbol
R
thJA
R
thJC
Typical
34
3
Maximum
40
4
Unit
°C/W
Notes:
a. Package limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See Solder Profile (
http://www.vishay.com/ppg?73257
). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 90 °C/W.
Document Number: 69827
S-81448-Rev. B, 23-Jun-08
www.vishay.com
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