OSD PRESSOR FOR MONITOR (PRELIMINARY)
S5D2510
PRODUCT SUMMARY
INTRODUCTION
S5D2510 is a stand-alone OSD Processor, which is used to display monitor adjustment or status information as a
certain character or symbol on screen. Its basic operation includes making the R/ G/ B signal for the character or
symbol by controlling the internal memory, synchronizing it with the horizontal flyback signal, and mixing it with
the main video signal in the video AMP IC. The font data for making the character or symbol is stored in the
internal ROM. It is accessed and controlled by the control data, transmitted from the micro controller through the
I
2
C bus. The chip contains internal PLL circuitry, so all timing control signals, including the system clock, are
synchronized with the horizontal flyback signal.
FEATURES
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General Font Matrix : 12
×
18
Fully Programmable Display Area : 15 Rows
×
30 Columns
Popular MCU Interface : I
2
C Protocol
Built in 1K-byte SRAM
Selectable Character Color (Up to 16 Color) : Font basis
Selectable Raster Color (Up to 16 Color) : Font basis
Programmable and Auto-adjustable Vertical Height of Character : Range 18
63
Character Blinking and Shadowing : Font basis
Programmable Symmetrical Row to Row Spacing : Range 0
31
Horizontal Starting Position : 256 different positions (6 dots for each step)
Vertical Starting Position : 256 different positions (4 scan line for each step)
Scrolling : Effect where 1 character line is scrolled up or down
4 Programmable Window Function and Window Priority Control
Selectable Window Shadow Width : H/ V 2, 4, 6 and 8 Dots
Supports Background Video Transparency : Font basis or Window basis
Full White Pattern Generation for Manufacturing Mode
Auto Character Height Control
Full-Screen Display RAM Erasing
OSD Vertical Bouncing Auto-Detecting & Correction
Enough font to support multiple language :
Wide Operating (Horizontal) Frequency Range : 30kHz
120kHz
640, 800, 1024 and 1280 Dots/ Line
Pixel Frequency provided by On-Chip PLL : 19.2MHz
153.6MHz
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S5D2510
OSD PROCESSOR FOR MONITOR (PRELIMINARY)
BLOCK DIAGRAM
The OSD Processor consists of 8 blocks on the top level as shown "Figure 1: Functional block diagram".
There are 4 input signals for the OSD Processor, which are serial data (SDA), clock (SCL) form a micro controller
and sync signals (HFLB and VFLB) from the H/ V sync processor. Through the serial data line, all information for
the OSD operation are transferred. Here, the protocol is I
2
C bus.
The data receiver block is a decoder for decoding the serial input data from a micro controller. The serial data is
converted to a 16-bit parallel format at the data receiver block. The parallel data are transported to the RAM or
registers by the bus line. The internal bus is a kind of star-bus type.
Control data comes from the data receiver is used to generate the control signals that control the character size,
character position, blank mode, blink mode, background color, and etc, in timing controller and display unit block.
All timing signals to read/ write data from/ to the internal RAM and ROM are also generated in the timing
controller block. In the PLL block, the internal system clock that is synchronized with HFLB is generated, which is
used as a timing reference signal for the OSD processor.
SDA
SCL
7
Data Receiver
(IIC Controller)
8
16
RAM
Data
/
16
Control
Data
Display RAM
(1K-Byte SRAM)
ROM
Address
/
9
Single
Color
ROM
(448X18X12)
Multi
Color
ROM
(16X3X18X12)
Control Register
/
Font
Control
Font
Data
Font
Data
12
Frame
Control
12
/
/
15
Display
Controller
14
Output Stage
13
12
11
H/V/CLK
Control
H/V/CLK
Control
INT
R_OUT
G_OUT
B_OUT
FBLK
Row
Control
Display
Control
HFLB
VFLB
6
OSD PLL
9
CLK
H-Pulse
V-Pulse
Frame
Control
Row
Control
Timing
Controller
2
VCO_IN
3
VREF
4
VICTL
1
VSSA
5
VDDA
10
VSS
16
VDD
Figure 1. Functional Block Diagram
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OSD PRESSOR FOR MONITOR (PRELIMINARY)
S5D2510
PIN CONFIGURATIONS
Package Type of the S5D2510 is 16-DIP-300.
Pin Configuration is shown in the figure bellow.
VSS_A
VCO_IN
VREF
VICTL
VDD_A
HFLB
SDA
SCL
1
2
3
4
16
15
14
13
VDD_D
INT
R_OUT
G_OUT
B_OUT
FBLK
VSS_D
VFLB
S5D2510
5
6
7
8
12
11
10
9
Figure 2. Pin configuration
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S5D2510
OSD PROCESSOR FOR MONITOR (PRELIMINARY)
PIN DESCRIPTIONS
Table 1. Pin Description
Pin No.
1
Signal
VSSA
Active
-
I/ O
-
Description
This pin provides the signal ground to the PLL circuit. We
recommend that you separate the analog ground from the digital
ground as shown in 'Figure 3 : S5D2510 Application Circuit' (6p)
for optimum performance (S5D2510's built-in PLL is sensitive to
noise due to wide range PLL characteristics).
This voltage is made in an external loop filter and sent to VCO's
input block. Operation voltage range is about 1
4V, and you
can raise immunity against external noise if you want lower the
VCO sensitivity by allowing the max operation voltage range
possible at 5V power voltage. Refer to 'PLL Control' (29p).
Connect to ground using resistance in order to make the
reference current that need to operate internal PLL (PLL region
control). Refer to 'PLL Control' (29p)'.
PLL gain controlled by controlling VCO Current.
This pin supplies +5V supply voltage to the PLL circuit. We
recommend that you divide the digital and analog power for PLL
as you did in 'Figure 3 : S5D2510 Application Circuit (6p)' to
prevent the influence of clock noise on the digital block.
Horizontal Flyback : This pin is reference signal source of the
internal PLL.
Serial Data (I
2
C). We recommend that you use the serial resistor
about 1/ 10 value of 5V pull-up resistor as I
2
C protocol.
Serial Clock (I
2
C). We recommend that you use the serial resistor
about 1/ 10 value of 5V pull-up resistor as I
2
C protocol.
Vertical Flyback signal : Similar to pin #6, this inputs the negative
polarity vertical flyback signal for syncronizing the vertical control
circuit.
Ground for Digital Part
Fast Blank Signal : OSD R/ G/ B output is recognized in the Pre-
AMP only when this output pin is high. In other words, if FBLK is
low, the OSD R/ G/ B output is not selected in the Pre-AMP.
OSD Signal Output (B).
OSD Signal Output (G)
OSD Signal Output (R)
2
VCO_IN
-
-
3
VREF
-
-
4
5
VICTL
VDDA
-
-
-
-
6
7
8
9
HFLB
SDA
SCL
VFLB
LOW
-
-
LOW
Input
In/ Out
In/ Out
Input
10
11
VSS
FBLK
-
-
-
Output
12
13
14
B_OUT
G_OUT
R_OUT
-
-
-
Output
Output
Output
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OSD PRESSOR FOR MONITOR (PRELIMINARY)
S5D2510
Table 1. Pin Description (Continued)
Pin No.
15
Signal
INT
Active
-
I/ O
Output
Description
This output pin signifies the color intensity. If you set the intensity
control bit to '1' (high) and use with the Pre-AMP supporting
intensity function, this pin outputs logic high while the specified
character or raster is being displayed. If this pin's output is high,
the color level is reduced to half and shows a difference in color
level from when it is low, allowing a 16-color choice when this
intensity pin and R/ G/ B output are combined. For example, if R,
G, B are all high, white is output. If you set the INT bit to '1' (high),
the color level becomes reduced to half and outputs gray.
+5V Supply Voltage for Digital Part
16
VDD
-
Output
* In the table above, only HFLB and VFLB's active column is low. This means that HFLB and VFLB are set so
that they are inputted as active low in default. For more information, please refer to 'Register Descriptions (13p)'.
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