EEWORLDEEWORLDEEWORLD

Part Number

Search

D-SUB-205AJ25SDTDB103

Description
D Type Connector, 25 Contact(s), Female, 0.109 inch Pitch, Solder Terminal, #4-40, Plug
CategoryThe connector    The connector   
File Size124KB,1 Pages
ManufacturerPalPilot
Download Datasheet Parametric View All

D-SUB-205AJ25SDTDB103 Overview

D Type Connector, 25 Contact(s), Female, 0.109 inch Pitch, Solder Terminal, #4-40, Plug

D-SUB-205AJ25SDTDB103 Parametric

Parameter NameAttribute value
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresROHS COMPLIANT,HEX-SCREWS
body width0.492 inch
subject depth0.492 inch
body length2.091 inch
Body/casing typePLUG
Contact to complete cooperationAU ON NI
Contact completed and terminatedTIN OVER NICKEL
Contact point genderFEMALE
Contact materialCOPPER ALLOY
contact modeSTAGGERED
Contact resistance15 mΩ
Contact styleRND PIN-SKT
Dielectric withstand voltage1000VAC V
Insulation resistance3000000000 Ω
Insulator colorBLACK
insulator materialPOLYAMIDE
Manufacturer's serial number205
Plug contact pitch0.109 inch
Match contact row spacing0.112 inch
Installation option 1#4-40
Installation option 2RIVET
Installation methodRIGHT ANGLE
Installation typeBOARD
PCB row number2
Number of rows loaded2
Maximum operating temperature105 °C
Minimum operating temperature-55 °C
PCB contact patternSTAGGERED
PCB contact row spacing2.8448 mm
Plating thickness30u inch
Rated current (signal)3 A
GuidelineUL
reliabilityCOMMERCIAL
Shell surfaceTIN
Shell materialSTEEL
Terminal length0.125 inch
Terminal pitch2.7686 mm
Termination typeSOLDER
Total number of contacts25
High-speed AD data acquisition, asynchronous FIFO, or dual-port RAM
RT acts as an oscilloscope, FPGA collects data and sends it to STM32 for display. Experienced friends please give me some advice....
523335234 FPGA/CPLD
Modification of sensitive variable table after ISE VHDL synthesis
After synthesis, I added sensitive variables according to the warning, but the program does not run. I want to know, after synthesis, I must remove the latch according to the warning, but must I add s...
timdong FPGA/CPLD
An unavoidable problem in electronic product design—EMI pre-compliance testing and debugging
EMI pre-compliance test and debugging have become an unavoidable problem for engineers in electronic product design.It is difficult to pass the expensive EMI compliance test in one go.It is difficult ...
肥兔子 Download Centre
Polling pin level
DSP INT1 pin is connected to the status input signal of external device. Now I need to judge whether INT1 level is high or low to execute other programs. I have not realized it by judging IFR bit. How...
ztttt2001 Embedded System
About 485
Hello everyone: I want to use 485 bus for transmission, but I am not familiar with 485. Can you give me some good methods and information? Email: dpjkf@163.com...
hargendazs Embedded System
What is the future of TI Stellaris, which has the same core as STM32?
In the past year, I guess the most mentioned thing by my friends is stm32. I remember reading Xiaolian's article. The key to the success of the promotion of microcontroller products lies in: Is the de...
soso stm32/stm8

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1891  2277  1628  490  1960  39  46  33  10  40 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号