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IDT71V424L10PHG

Description
Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44
Categorystorage    storage   
File Size71KB,9 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

IDT71V424L10PHG Overview

Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44

IDT71V424L10PHG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSOP2
package instruction0.400 INCH, ROHS COMPLIANT, TSOP2-44
Contacts44
Reach Compliance Codecompli
ECCN code3A991.B.2.A
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G44
JESD-609 codee3
length18.41 mm
memory density4194304 bi
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals44
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP44,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.01 A
Minimum standby current3 V
Maximum slew rate0.165 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
Base Number Matches1
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
Features
IDT71V424S
IDT71V424L
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
A
0
A
18
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
I/O CONTROL
8
8
WE
OE
CS
CONTROL
LOGIC
3622 drw 01
JULY 2004
1
©2004 Integrated Device Technology, Inc.
DSC-3622/06

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