EDJ4208EASE-DJ-F datasheet, PDF

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EDJ4208EASE-DJ-F: DescriptionDDR DRAM, 512MX8, 0.255ns, CMOS, PBGA78,; Categorystorage storage; File Size2MB，146 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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EDJ4208EASE-DJ-F Overview

DDR DRAM, 512MX8, 0.255ns, CMOS, PBGA78,

EDJ4208EASE-DJ-F Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
package instruction	FBGA, BGA78,9X13,32
Reach Compliance Code	compli
Maximum access time	0.255 ns
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B78
memory density	4294967296 bi
Memory IC Type	DDR DRAM
memory width	8
Number of terminals	78
word count	536870912 words
character code	512000000
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA78,9X13,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	1.35 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	4,8
Maximum standby current	0.02 A
Maximum slew rate	0.325 mA
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Base Number Matches	1

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DATA SHEET

4G bits DDR3L SDRAM

EDJ4204EASE (1024M words

4 bits)

EDJ4208EASE (512M words

8 bits)

Specifications

•

Density: 4G bits

•

Organization



128M words

4 bits

8 banks (EDJ4204EASE)



64M words

8 bits

8 banks (EDJ4208EASE)

•

Package



78-ball FBGA



Lead-free (RoHS compliant) and Halogen-free

•

Power supply: 1.35V (typ.)



VDD, VDDQ

1.283V to 1.45V



Backward compatible for VDD, VDDQ

1.5V

0.075V

•

Data rate



1333Mbps/1066Mbps (max.)

•

1KB page size



Row address: A0 to A15



Column address: A0 to A9, A11 (EDJ4204EASE)

A0 to A9 (EDJ4208EASE)

•

Eight internal banks for concurrent operation

•

Burst lengths (BL): 8 and 4 with Burst Chop (BC)

•

Burst type (BT):



Sequential (8, 4 with BC)



Interleave (8, 4 with BC)

•

/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

•

/CAS Write Latency (CWL): 5, 6, 7, 8

•

Precharge: auto precharge option for each burst

access

•

Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

•

Refresh: auto-refresh, self-refresh

•

Refresh cycles



Average refresh period

7.8µs at 0°C

≤

≤ +85°C

3.9µs at

+85°C <

≤ +95°C

•

Operating case temperature range



TC = 0°C to +95°C

Features

•

Double-data-rate architecture: two data transfers per

clock cycle

•

The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

•

Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

•

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

•

Posted /CAS by programmable additive latency for

better command and data bus efficiency

•

On-Die Termination (ODT) for better signal quality



Synchronous ODT



Dynamic ODT



Asynchronous ODT

•

Multi Purpose Register (MPR) for pre-defined pattern

read out

•

ZQ calibration for DQ drive and ODT

•

Programmable Partial Array Self-Refresh (PASR)

•

/RESET pin for Power-up sequence and reset

function

•

SRT range:



Normal/extended

•

Programmable Output driver impedance control

Document No. E1727E41 (Ver. 4.1)

Date Published September 2011 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2010-2011

EDJ4204EASE, EDJ4208EASE

CONTENTS

Specifications.................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electrical Conditions ......................................................................................................................................6

Absolute Maximum Ratings .........................................................................................................................6

Operating Temperature Condition ...............................................................................................................6

Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V) ...............7

AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V)...................7

VREF Tolerances ........................................................................................................................................8

Input Slew Rate Derating .............................................................................................................................9

AC and DC Logic Input Levels for Differential Signals ............................................................................... 15

AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V) .............. 20

AC Overshoot/Undershoot Specification.................................................................................................... 22

Output Driver Impedance........................................................................................................................... 23

On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................25

ODT Timing Definitions.............................................................................................................................. 27

IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V) ............................... 31

Electrical Specifications...............................................................................................................................44

DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V) ............................................. 44

Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.283V to 1.45V) ................................................................. 46

Standard Speed Bins ................................................................................................................................. 47

AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V, VSS, VSSQ = 0V)................... 49

Block Diagram .............................................................................................................................................62

Pin Function.................................................................................................................................................63

Command Operation ...................................................................................................................................65

Command Truth Table ............................................................................................................................... 65

CKE Truth Table ........................................................................................................................................ 69

Simplified State Diagram .............................................................................................................................70

RESET and Initialization Procedure ............................................................................................................71

Power-Up and Initialization Sequence ....................................................................................................... 71

Reset and Initialization with Stable Power ................................................................................................. 72

Programming the Mode Register.................................................................................................................73

Mode Register Set Command Cycle Time (tMRD) ....................................................................................73

MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 73

DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 74

DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 75

DDR3 SDRAM Mode Register 2 [MR2] ..................................................................................................... 76

Data Sheet E1727E41 (Ver. 4.1)

EDJ4204EASE, EDJ4208EASE

DDR3 SDRAM Mode Register 3 [MR3] ..................................................................................................... 77

Burst Length (MR0) ................................................................................................................................... 78

Burst Type (MR0) ...................................................................................................................................... 78

DLL Enable (MR1) ..................................................................................................................................... 79

DLL-off Mode ............................................................................................................................................. 79

DLL on/off switching procedure ................................................................................................................. 80

Additive Latency (MR1).............................................................................................................................. 82

Write Leveling (MR1) ................................................................................................................................. 83

TDQS, /TDQS function (MR1) ................................................................................................................... 86

Extended Temperature Usage (MR2) ........................................................................................................ 87

Multi Purpose Register (MR3).................................................................................................................... 89

Operation of the DDR3 SDRAM ..................................................................................................................96

Read Timing Definition............................................................................................................................... 96

Read Operation ....................................................................................................................................... 100

Write Timing Definition............................................................................................................................. 107

Write Operation........................................................................................................................................ 108

Write Timing Violations ............................................................................................................................ 114

Write Data Mask ...................................................................................................................................... 115

Precharge ................................................................................................................................................ 116

Auto Precharge Operation ....................................................................................................................... 117

Auto-Refresh............................................................................................................................................ 118

Self-Refresh............................................................................................................................................. 119

Power-Down Mode .................................................................................................................................. 121

Input Clock Frequency Change during Precharge Power-Down.............................................................. 128

On-Die Termination (ODT)....................................................................................................................... 129

ZQ Calibration.......................................................................................................................................... 141

Package Drawing ......................................................................................................................................143

78-ball FBGA ........................................................................................................................................... 143

Recommended Soldering Conditions........................................................................................................144

Data Sheet E1727E41 (Ver. 4.1)

EDJ4208EASE-DJ-F Related Products

	EDJ4208EASE-DJ-F	EDJ4204EASE-AE-F
Description	DDR DRAM, 512MX8, 0.255ns, CMOS, PBGA78,	DDR DRAM, 1GX4, 0.3ns, CMOS, PBGA78,
Is it Rohs certified?	conform to	conform to
Maker	Micron Technology	Micron Technology
package instruction	FBGA, BGA78,9X13,32	FBGA, BGA78,9X13,32
Reach Compliance Code	compli	compliant
Maximum access time	0.255 ns	0.3 ns
Maximum clock frequency (fCLK)	667 MHz	533 MHz
I/O type	COMMON	COMMON
interleaved burst length	4,8	4,8
JESD-30 code	R-PBGA-B78	R-PBGA-B78
memory density	4294967296 bi	4294967296 bit
Memory IC Type	DDR DRAM	DDR DRAM
memory width	8	4
Number of terminals	78	78
word count	536870912 words	1073741824 words
character code	512000000	1000000000
Maximum operating temperature	85 °C	85 °C
organize	512MX8	1GX4
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	FBGA
Encapsulate equivalent code	BGA78,9X13,32	BGA78,9X13,32
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH
power supply	1.35 V	1.35 V
Certification status	Not Qualified	Not Qualified
refresh cycle	8192	8192
Continuous burst length	4,8	4,8
Maximum standby current	0.02 A	0.02 A
Maximum slew rate	0.325 mA	0.32 mA
Nominal supply voltage (Vsup)	1.35 V	1.35 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal form	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM

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