AD5331BRUZ-REEL71 datasheet, PDF

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AD5331BRUZ-REEL71: Description2.5 V to 5.5 V, 115 Î¼A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs; File Size530KB，28 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD5331BRUZ-REEL71 Overview

2.5 V to 5.5 V, 115 Î¼A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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2.5 V to 5.5 V, 115 μA, Parallel Interface

Single Voltage-Output 8-/10-/12-Bit DACs

AD5330/AD5331/AD5340/AD5341

FEATURES

AD5330: single 8-bit DAC in 20-lead TSSOP

AD5331: single 10-bit DAC in 20-lead TSSOP

AD5340: single 12-bit DAC in 24-lead TSSOP

AD5341: single 12-bit DAC in 20-lead TSSOP

Low power operation: 115 μA @ 3 V, 140 μA @ 5 V

Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin

2.5 V to 5.5 V power supply

Double-buffered input logic

Guaranteed monotonic by design over all codes

Buffered/unbuffered reference input options

Output range: 0 V to V

REF

or 0 V to 2 × V

REF

Power-on reset to 0 V

Simultaneous update of DAC outputs via LDAC pin

Asynchronous CLR facility

Low power parallel data interface

On-chip rail-to-rail output buffer amplifiers

Temperature range: −40°C to +105°C

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD5341

are single 8-/10-/12-

bit DACs. They operate from a 2.5 V to 5.5 V supply consuming

just 115 μA at 3 V and feature a power-down mode that further

reduces the current to 80 nA. The devices incorporate an on-chip

output buffer that can drive the output to both supply rails, but

the AD5330, AD5340, and AD5341 allow a choice of buffered

or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel

interface. CS selects the device and data is loaded into the

input registers on the rising edge of WR.

The GAIN pin allows the output range to be set at 0 V to V

REF

0 V to 2 × V

REF

Input data to the DACs is double-buffered, allowing simultane-

ous update of multiple DACs in a system using the LDAC pin.

An asynchronous CLR input is also provided, which resets the

contents of the input register and the DAC register to all zeros.

These devices also incorporate a power-on reset circuit that

ensures that the DAC output powers on to 0 V and remains

there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in thin

shrink small outline packages (TSSOP).

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Industrial process control

Protected by U.S. Patent Number 5,969,657.

FUNCTIONAL BLOCK DIAGRAM

REF

POWER-ON

RESET

AD5330

BUF

GAIN

INTERFACE LOGIC

INPUT

DAC

7 20

0 13

CLR

LDAC

8-BIT

DAC

BUFFER

OUT

RESET

POWER-DOWN

LOGIC

GND

Figure 1. AD5330

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

06852-001

AD5330/AD5331/AD5340/AD5341

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Terminology .................................................................................... 11

Typical Performance Characteristics ........................................... 13

Theory of Operation ...................................................................... 17

Digital-to-Analog Section ......................................................... 17

Resistor String ............................................................................. 17

DAC Reference Input ................................................................. 17

Output Amplifier ........................................................................ 17

Parallel Interface ............................................................................. 18

Double-Buffered Interface ........................................................ 18

Clear Input (CLR) ...................................................................... 18

Chip Select Input (CS) ............................................................... 18

Write Input (WR) ....................................................................... 18

Load DAC Input (LDAC) .......................................................... 18

High-Byte Enable Input (HBEN) ............................................. 18

Power-On Reset .......................................................................... 18

Power-Down Mode ........................................................................ 19

Suggested Databus Formats .......................................................... 20

Applications Information .............................................................. 21

Typical Application Circuits ..................................................... 21

Driving V

From the Reference Voltage ............................... 21

Bipolar Operation Using the AD5330/AD5331/

AD5340/AD5341 ......................................................................... 21

Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21

Programmable Current Source ................................................ 22

Power Supply Bypassing and Grounding ................................ 22

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 25

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Changes to Table 4 .......................................................................... 16

Replaced Driving V

from the Reference Voltage Section ..... 21

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 25

4/00—Revision 0: Initial Version

Rev. A | Page 2 of 28

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