TS68EN360VR33L datasheet, PDF - EEWORLD Datasheet

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TS68EN360VR33L: DescriptionRISC PROCESSOR, CPGA241; CategoryThe embedded processor and controller Microcontrollers and processors; File Size856KB，82 Pages; ManufacturerAtmel (Microchip)

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TS68EN360VR33L Overview

RISC PROCESSOR, CPGA241

TS68EN360VR33L Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	PGA
package instruction	PGA, PGA241M,18X18
Contacts	241
Reach Compliance Code	unknow
ECCN code	3A991.A.2
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	33 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-CPGA-P241
JESD-609 code	e0
length	47.245 mm
low power mode	YES
Number of terminals	241
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA241M,18X18
Package shape	SQUARE
Package form	GRID ARRAY
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.96 mm
speed	33 MHz
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	47.245 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Features

•

CPU32+ Processor (4.5 MIPS at 25 MHz)

– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)

– Background Debug Mode

– Byte-misaligned Addressing

Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)

Up to 32 Address Lines (At Least 28 Always Available)

Complete Static Design (0 - 25 MHz Operation)

Slave Mode to Disable CPU32+ (Allows Use with External Processors)

– Multiple QUICCs Can Share One System Bus (One Master)

– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and

Intelligent Peripheral (22 MIPS at 25 MHz)

– Peripheral Device of TSPC603e (see DC415/D note)

Four General-purpose Timers

– Superset of MC68302 Timers

– Four 16-bit Timers or Two 32-bit Timers

– Gate Mode Can Enable/Disable Counting

Two Independent DMAs (IDMAs)

System Integration Module (SIM60)

Communications Processor Module (CPM)

Four Baud Rate Generators

Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)

Two SMC

= +5V ± 5%

max

= 25 MHz and 33 MHz

Military Temperature Range: -55°C < T

< +125°C

= 1.4 W at 25 MHz; 5.25V

2 W at 33 MHz; 5.25V

•

32-bit Quad

Integrated

Communication

Controller

TS68EN360

Description

The TS68EN360 QUad Integrated Communication Controller (QUICC

™

) is a versatile

one-chip integrated microprocessor and peripheral combination that can be used in a

variety of controller applications. It particularly excels in communications activities.

The QUICC (pronounced “quick”) can be described as a next-generation TS68302

with higher performance in all areas of device operation, increased flexibility, major

extensions in capability, and higher integration. The term “quad” comes from the fact

that there are four serial communications controllers (SCCs) on the device; however,

there are actually seven serial channels: four SCCs, two serial management control-

lers (SMCs), and one serial peripheral interface (SPI).

Screening/Quality

This product is manufactured in full compliance with:

•

MIL-STD-883 (class B)

QML (class Q)

or according to Atmel standards

Rev. 2113A–HIREL–03/02

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