DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD720110A
USB2.0 HUB CONTROLLER
The
µ
PD720110A is an USB 2.0 hub device that comply with the Universal Serial Bus (USB) Specification Revision
2.0 and work up to 480 Mbps. USB2.0 compliant transceivers are integrated for upstream and all downstream ports.
The
µ
PD720110A works backward compatible either when any one of downstream ports is connected to an USB 1.1
compliant device, or when the upstream port is connected to a USB 1.1 compliant host.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µ
PD720110A User’s Manual: S15738E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
• Certified by USB implementers forum and granted with USB 2.0 high-Speed Logo
• High-speed or full-speed packet protocol sequencer for Endpoint 0/1
• 4 (Max.) downstream facing ports
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Supports split transaction to handle full-speed and low-speed transaction at downstream facing ports when Hub
controller is working at high-speed mode.
• One Transaction Translator per Hub and supports 4 non-periodic buffers
• Supports self-powered mode only
• Supports Over-current detection and Individual power control
• Supports configurable vendor ID and product ID with external Serial ROM
• Supports “non-removable” attribution on individual port
• Uses 30 MHz X’tal, 30 MHz clock input, or 48 MHz clock input
• Supports downstream port status with LED
• HS detection indicator output
• 3.3 V power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15737EJ5V0DS00 (5th edition)
Date Published August 2004 NS CP (N)
Printed in Japan
NEC Electronics Corporation 2004
µ
PD720110A
ORDERING INFORMATION
Part Number
Package
100-pin plastic LQFP (Fine pitch) (14
×
14)
µ
PD720110AGC-8EA
BLOCK DIAGRAM
To Host/Hub
downstream
facing port
Upstream facing port
UP_PHY
CDR
SERDES
UPC
FS_REP
SIE_2H
ALL_TT
F_TIM
EP1
EP0
External
Serial ROM
ROM I/F
ROM
CDR
DP(1)_PHY
Downstream facing port #1
DP(2)_PHY
Downstream facing port #2
DP(3)_PHY
Downstream facing port #3
To Hub/Function
upstream facing port
To Hub/Function
upstream facing port
To Hub/Function
upstream facing port
To Hub/Function
upstream facing port
DPC
APLL
CLKSEL
X1_CLK/X2
OSB
DP(4)_PHY
Downstream facing port #4
PPB(4:1)
CSB(4:1)
2
Data Sheet S15737EJ5V0DS
µ
PD720110A
APLL
ALL_TT
: Generates all clocks of Hub.
: Translates the high-speed transactions (split transactions) for full/low-speed device
to full/low-speed transactions.
ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.
CDR
DPC
DP(n)_PHY
EP0
EP1
F_TIM (Frame Timer)
: Data & clock recovery circuit
: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and
Resume
: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and
low-speed (1.5 Mbps) transaction
: Endpoint 0 controller
: Endpoint 1 controller
: Manages hub’s synchronization by using micro-SOF which is received at upstream
port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.
FS_REP
OSB
ROM
ROM I/F
SERDES
SIE_2H
UP_PHY
UPC
: Full/low-speed repeater is enabled when the
µ
PD720110A is worked at full-speed
mode
: Oscillator Block
: Contains default Descriptors
: Interface block for external Serial ROM which contains user-defined Descriptors
: Serializer and Deserializer
: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer
: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)
transaction
: Upstream Port Controller handles Suspend and Resume
Data Sheet S15737EJ5V0DS
3
µ
PD720110A
PIN CONFIGURATION (TOP VIEW)
•
100-pin plastic LQFP (Fine pitch) (14
×
14)
µ
PD720110AGC-8EA
100
95
90
85
80
V
DD
V
SS
X1_CLK
X2
V
DD
PLLLOCK
OSL
TS1
CLKSEL
TS2
TS3
TS4
TS5
TS6
SYSRSTB
V
SS
TS7
TS8
TSO
SMD
TS9
TS10
SCL
SDA
V
DD
1
76
V
SS
RSDPD4
DPD4
V
DD
DMD4
RSDMD4
V
SS
RSDPD3
DPD3
V
DD
DMD3
RSDMD3
V
SS
RSDPD2
DPD2
V
DD
DMD2
RSDMD2
V
SS
RSDPD1
DPD1
V
DD
DMD1
RSDMD1
V
SS
75
5
70
10
65
15
60
20
55
25
51
V
DD
RPU
V
SS
RSDPU
DPU
V
DD
DMU
RSDMU
V
SS
PC1
AV
SS
PC2
AV
DD
AV
SS
V
SS
N.C.
RREF
AV
SS
AV
DD
AV
SS
CLK30MO
EPERR
PORTRMV4
PORTRMV3
V
DD
26
30
35
40
4
V
SS
PWMODE
NUMPORT
VBUSM
PORTRMV1
PORTRMV2
CSB1
CSB2
CSB3
CSB4
V
SS
PPB1
PPB2
PPB3
PPB4
HSMODE
AMBERBP1
GREENBP1
AMBERBP2
GREENBP2
AMBERBP3
GREENBP3
AMBERBP4
GREENBP4
V
SS
Data Sheet S15737EJ5V0DS
45
50
µ
PD720110A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin Name
V
DD
V
SS
X1_CLK
X2
V
DD
PLLLOCK
OSL
TS1
CLKSEL
TS2
TS3
TS4
TS5
TS6
SYSRSTB
V
SS
TS7
TS8
TSO
SMD
TS9
TS10
SCL
SDA
V
DD
Pin No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
V
SS
PWMODE
NUMPORT
VBUSM
PORTRMV1
PORTRMV2
CSB1
CSB2
CSB3
CSB4
V
SS
PPB1
PPB2
PPB3
PPB4
HSMODE
AMBERBP1
GREENBP1
AMBERBP2
GREENBP2
AMBERBP3
GREENBP3
AMBERBP4
GREENBP4
V
SS
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin Name
V
DD
PORTRMV3
PORTRMV4
EPERR
CLK30MO
AV
SS
AV
DD
AV
SS
RREF
N.C.
V
SS
AV
SS
AV
DD
PC2
AV
SS
PC1
V
SS
RSDMU
DMU
V
DD
DPU
RSDPU
V
SS
RPU
V
DD
Pin No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
V
SS
RSDMD1
DMD1
V
DD
DPD1
RSDPD1
V
SS
RSDMD2
DMD2
V
DD
DPD2
RSDPD2
V
SS
RSDMD3
DMD3
V
DD
DPD3
RSDPD3
V
SS
RSDMD4
DMD4
V
DD
DPD4
RSDPD4
V
SS
Data Sheet S15737EJ5V0DS
5
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