DATASHEET
ISLA212P
12-Bit, 250MSPS/200MSPS/130MSPS ADC
The ISLA212P is a series of low power, high performance
12-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the series supports sampling rates of up to 250MSPS.
The ISLA212P is part of a pin-compatible family of 12 to 16-bit
A/Ds with maximum sample rates ranging from 130MSPS to
500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset. Digital output data is presented in
selectable LVDS or CMOS formats, and can be configured as
full-width, single data rate (SDR) or half-width, double data
rate (DDR). The ISLA212P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
FN7717
Rev 2.00
November 30, 2012
Features
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Selectable Clock Divider
Key Specifications
• SNR @ 250/200/130MSPS
70.5/71.0/71.5dBFS f
IN
= 30MHz
68.7/68.9/68.8dBFS f
IN
= 363MHz
• SFDR @ 250/200/130MSPS
83/83/88dBc f
IN
= 30MHz
78/81/85dBc f
IN
= 363MHz
• Total Power Consumption = 440mW @ 250MSPS
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKDIVRSTN
CLKDIVRSTP
Pin-Compatible Family
OVDD
CLKDIV
AVDD
MODEL
ISLA216P25
ISLA216P20
CLKOUTP
CLKOUTN
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
CLKP
CLKN
CLOCK
MANAGEMENT
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
VINP
SHA
VINN
12-BIT
250 MSPS
ADC
DIGITAL
ERROR
C R E TIO
ORC N
SPI
CONTROL
D[11:0]P
D[11:0]N
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
VCM
+
–
NAPSLP
RESETN
FN7717 Rev 2.00
November 30, 2012
RLVDS
OVSS
AVSS
CSB
SCLK
SDIO
SDO
Page 1 of 36
ISLA212P
Pin Configuration - LVDS MODE
ISLA212P
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
ORN
ORP
SDO
DNC
DNC
DNC
DNC
CSB
D0N
55
54 D1P
53 D1N
52 D2P
51 D2N
50 D3P
49 D3N
48 CLKOUTP
47 CLKOUTN
46 RLVDS
45 OVSS
44 D4P
43 D4N
42 D5P
41 D5N
40 D6P
39 D6N
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
38 D7P
37 D7N
19
AVDD
20
AVDD
21
AVDD
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
D11N
29
D11P
30
D10N
31
D10P
32
OVDD
33
D9N
34
D9P
35
D8N
36
D8P
D0P
56
72
DNC
DNC
NAPSLP
VCM
AVSS
AVDD
AVSS
VINN
VINN
1
2
3
4
5
6
7
8
9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VINP 10
VINP 11
AVSS 12
AVDD 13
AVSS 14
CLKDIV 15
IPTAT 16
DNC 17
Connect Thermal Pad to AVSS
RESETN 18
FN7717 Rev 2.00
November 30, 2012
Page 2 of 36
ISLA212P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
1, 2, 17, 57, 58, 59, 60
6, 13, 19, 20, 21, 70, 71,
72
5, 7, 12, 14
27, 32, 62
26, 45, 61, 65
3
4
8, 9
10, 11
15
16
18
22, 23
24, 25
28
29
30
31
33
34
35
36
37
38
39
40
41
42
43
44
46
47, 48
49
50
51
52
53
54
55
56
63, 64
LVDS PIN NAME
DNC
AVDD
AVSS
OVDD
OVSS
NAPSLP
VCM
VINN
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D11N
D11P
D10N
D10P
D9N
D9P
D8N
D8P
D7N
D7P
D6N
D6P
D5N
D5P
D4N
D4P
RLVDS
CLKOUTN, CLKOUTP
D3N
D3P
D2N
D2P
D1N
D1P
D0N
D0P
ORN, ORP
Do Not Connect
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Analog Input Negative
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute
temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bit 11(MSB) Output Complement
LVDS Bit 11 (MSB) Output True
LVDS Bit 10 Output Complement
LVDS Bit 10 Output True
LVDS Bit 9 Output Complement
LVDS Bit 9 Output True
LVDS Bit 8 Output Complement
LVDS Bit 8 Output True
LVDS Bit 7 Output Complement
LVDS Bit 7 Output True
LVDS Bit 6 Output Complement
LVDS Bit 6 Output True
LVDS Bit 5 Output Complement
LVDS Bit 5 Output True
LVDS Bit 4 Output Complement
LVDS Bit 4 Output True
LVDS Bias Resistor (Connect to OVSS with 1% 10k)
LVDS Clock Output Complement, True
LVDS Bit 3 Output Complement
LVDS Bit 3 Output True
LVDS Bit 2 Output Complement
LVDS Bit 2 Output True
LVDS Bit 1 Output Complement
LVDS Bit 1 Output True
LVDS Bit 0 Output Complement
LVDS Bit 0 Output True
LVDS Over Range Complement, True
NC in DDR Mode
NC in DDR Mode
DDR Logical Bits 2, 3
DDR Logical Bits 2, 3
NC in DDR Mode
NC in DDR Mode
DDR Logical Bits 0, 1
DDR Logical Bits 0, 1
DDR Over Range
NC in DDR Mode
NC in DDR Mode
DDR Logical Bits 10, 11
DDR Logical Bits 10, 11
NC in DDR Mode
NC in DDR Mode
DDR Logical Bits 8, 9
DDR Logical Bits 8, 9
NC in DDR Mode
NC in DDR Mode
DDR Logical Bits 6, 7
DDR Logical Bits 6, 7
NC in DDR Mode
NC in DDR Mode
DDR Logical Bits 4, 5
DDR Logical Bits 4, 5
LVDS PIN FUNCTION
DDR MODE COMMENTS
FN7717 Rev 2.00
November 30, 2012
Page 3 of 36
ISLA212P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
66
67
68
69
Exposed Paddle
LVDS PIN NAME
SDO
CSB
SCLK
SDIO
AVSS
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
(Continued)
DDR MODE COMMENTS
LVDS PIN FUNCTION
Pin Configuration - CMOS MODE
ISLA212P
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
DNC
DNC
DNC
DNC
DNC
DNC
55
54 D1
53 DNC
52 D2
51 DNC
50 D3
49 DNC
48 CLKOUT
47 DNC
46 RLVDS
45 OVSS
44 D4
43 DNC
42 D5
41 DNC
40 D6
39 DNC
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
38 D7
37 DNC
29
D11
30
DNC
31
D10
32
OVDD
33
DNC
34
D9
35
DNC
36
D8
SDO
CSB
OR
D0
56
72
DNC
DNC
NAPSLP
VCM
AVSS
AVDD
AVSS
VINN
VINN
1
2
3
4
5
6
7
8
9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VINP 10
VINP 11
AVSS 12
AVDD 13
AVSS 14
CLKDIV 15
IPTAT 16
DNC 17
RESETN 18
19
AVDD
20
AVDD
21
AVDD
Connect Thermal Pad to AVSS
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
DNC
FN7717 Rev 2.00
November 30, 2012
Page 4 of 36
ISLA212P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
1, 2, 17, 28, 30, 33, 35,
37, 39, 41, 43, 47, 49,
51, 53, 55, 57, 58, 59,
60, 63
6, 13, 19, 20, 21, 70, 71,
72
5, 7, 12, 14
27, 32, 62
26, 45, 61, 65
3
4
8, 9
10, 11
15
16
18
22, 23
24, 25
29
31
34
36
38
40
42
44
46
48
50
52
54
56
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
DNC
Do Not Connect
CMOS PIN FUNCTION
DDR MODE COMMENTS
AVDD
AVSS
OVDD
OVSS
NAPSLP
VCM
VINN
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Analog Input Negative
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute
temperature)
Power On Reset (Active Low)
Clock Input True, Complement
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
D11
D10
D9
D8
D7
D6
D5
D4
RLVDS
CLKOUT
D3
D2
D1
D0
OR
SDO
CSB
SCLK
SDIO
AVSS
CMOS Bit 11 (MSB) Output
CMOS Bit 10 Output
CMOS Bit 9 Output
CMOS Bit 8 Output
CMOS Bit 7 Output
CMOS Bit 6 Output
CMOS Bit 5 Output
CMOS Bit 4 Output
LVDS Bias Resistor (Connect to OVSS with 1% 10k)
CMOS Clock Output
CMOS Bit 3 Output
CMOS Bit 2 Output
CMOS Bit 1 Output
CMOS Bit 0 (LSB) Output
CMOS Over Range
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
NC in DDR Mode
DDR Logical Bits 2, 3
NC in DDR Mode
DDR Logical Bits 0, 1
DDR Over Range
NC in DDR Mode
DDR Logical Bits 10, 11
NC in DDR Mode
DDR Logical Bits 8, 9
NC in DDR Mode
DDR Logical Bits 6, 7
NC in DDR Mode
DDR Logical Bits 4, 5
FN7717 Rev 2.00
November 30, 2012
Page 5 of 36
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