®
XC73144
144-Macrocell CMOS EPLD
Product Specifications
Features
• High-Performance EPLD
– 7.5 ns pin-to-pin speed on all fast inputs
– 100 MHz maximum clock frequency
• Advanced Dual-Block architecture
– Four Fast Function Blocks
– Twelve High-Density Function Blocks
• 100% interconnect matrix
• High-Speed arithmetic carry network
– 1 ns ripple-carry delay per bit
– 43 MHz 16-bit accumulators
• 144 Macrocells with programmable I/O architecture
• Up to 132 inputs programmable as direct, latched, or
registered
• All outputs with 24 mA drive
• 3.3 V or 5 V I/O operation
• Meets JEDEC Standard (8-1A) for 3.3 V
±
0.3 V
• Power management options
• Multiple security bits for design protection
• 160-pin plastic quad flat pack and 225-pin ball-grid-
array packages
• 100% PCI compliant
• Programmable slew rate
• Programmable ground control
The Universal Interconnect Matrix connects the Function
Blocks to each other and to all input pins, providing 100%
connectivity between the Function Blocks. This allows
logic functions to be mapped into the Function Blocks and
interconnected without routing restrictions.
The XC73144 is designed in a 0.8
µ
CMOS EPROM tech-
nology.
In addition, the XC73144 includes a programmable power
management feature to specify high-performance or low-
power operation on an individual Macrocell-by-Macrocell
basis. Unused Macrocells are automatically turned off to
minimize power dissipation. Designers can operate
speed-critical paths at maximum performance, while non-
critical paths dissipate less power.
Xilinx development software (XEPLD) supports all mem-
bers of XC7300 family. The designer can create, imple-
ment, and verify digital logic circuits for EPLD devices
using the Xilinx XEPLD Development System. Designs
can be represented as schematics consisting of XEPLD
library components, as behavioral descriptions, or as a
mixture of both. The XEPLD translator automatically per-
forms logic optimization, collapsing, mapping and routing
without user intervention. After compiling the design,
XEPLD translator produces documentation for design
analysis and creates a programming file to configure the
device.
The following lists some of the XEPLD Development Sys-
tem features.
• Familiar design approach similar to TTL and PLD
techniques
• Converts netlist to fuse map in minutes using a 386/
486 PC or workstation platform
• Interfaces to standard third-party CAE schematics,
simulation tools, and behavioral languages
• Timing simulation using Viewsim, OrCAD VST, Mentor,
LMC and other tools compatible with the Xilinx Netlist
Format (XNF)
General Description
The XC73144 is a member of the Xilinx Dual-Block EPLD
family. It consists of four Fast Function Blocks and twelve
High-Density Function Blocks interconnected by a central
Universal Interconnect Matrix (UIM).
The sixteen Function Blocks in the XC73144 are PAL-like
structures, complete with programmable product term
arrays and programmable multilevel Macrocells. Each
Function Block receives 24 inputs, contains nine Macro-
cells configurable for registered or combinatorial logic and
produces nine outputs which feedback to the UIM and
output pins.
2-65
This document was created with FrameMaker 4 0 2
XC73144 Programmable Logic Device
PQ160
19
18
17
15
13
11
BG225
H1
H2
G1
G3
E1
F3
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
6
FFB1
6
FFB2
MC2-9
MC2-8
AND ARRAY
12
3
AND ARRAY
12
3
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
9
FFB4
FFB3
MC3-9
MC3-8
AND ARRAY
AND ARRAY
12
3
12
3
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
9
18
54
Arithmetic
FB16
Serial
Carry
Shift
FB5
MC5-9
MC5-8
AND ARRAY
AND ARRAY
MC5-7
MC5-6
MC5-5
MC5-4
MC5-3
MC5-2
MC5-1
FB15
FB6
MC6-9
MC6-8
AND ARRAY
AND ARRAY
MC6-7
MC6-6
MC6-5
MC6-4
MC6-3
MC6-2
MC6-1
FB14
FB7
MC7-9
MC7-8
AND ARRAY
AND ARRAY
MC7-7
MC7-6
MC7-5
MC7-4
MC7-3
MC7-2
MC7-1
FB13
FB8
MC8-9
MC8-8
AND ARRAY
AND ARRAY
MC8-7
MC8-6
MC8-5
MC8-4
MC8-3
MC8-2
MC8-1
FB12
FB9
MC9-9
MC9-8
AND ARRAY
AND ARRAY
MC9-7
MC9-6
MC9-5
MC9-4
MC9-3
MC9-2
MC9-1
FB11
FB10
MC10-9
MC10-8
AND ARRAY
AND ARRAY
MC10-7
MC10-6
MC10-5
MC10-4
MC10-3
MC10-2
MC10-1
Serial Shift
Arithmetic Carry
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
O
O
O
O
O
O
I/O/FI
I/O/FI
I/O/FI
O/FOE1
O/FOE0
O/CKEN1
O/CKEN0
O
O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
18
54
42
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
BG225
J1
K1
J2
K3
L2
N1
PQ160
22
23
24
26
28
30
12
12
12
36
44
47
49
54
56
58
59
60
N3
P4
P5
N6
P7
R6
P8
R8
N8
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
9
9
9
A7
A6
B7
C6
B5
A3
C5
A2
B1
142
143
144
146
148
152
154
156
4
53
–
52
–
39
–
38
–
–
N9
L4
M7
M5
L5
L6
M4
M6
M9
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
MC4-1
MC4-2
MC4-3
MC4-4
MC4-5
MC4-6
MC4-7
MC4-8
MC4-9
9
42
9
9
D5
D6
E5
E6
G4
E4
J4
F4
F5
149
–
150
–
3
–
5
–
–
105
107
109
112
114
123
125
128
116
130
147
151
153
155
158
129
133
145
25
27
33
35
42
34
32
29
37
–
–
–
–
–
65
66
83
85
62
63
64
86
88
68
71
73
75
77
79
82
90
92
95
97
98
101
F14
E15
D15
E13
B15
A14
C11
A12
C13
B10
A5
A4
B4
B3
C3
C10
A11
B6
K2
L1
N2
M3
P3
P1
L3
M1
P2
M10
L10
L12
K12
K11
L11
M11
J12
G12
K9
R10
P9
M14
N15
N10
R12
P12
P13
N12
P14
N14
M15
K14
J13
J15
H14
G13
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
MC16-1
MC16-2
MC16-3
MC16-4
MC16-5
MC16-6
MC16-7
MC16-8
MC16-9
21
21
K15
L15
K13
L14
L13
P15
N13
R14
N11
R13
R11
R7
P10
N7
P6
R4
N5
R2
F1
G2
F2
C1
D2
C2
B2
E2
E3
D7
D9
D12
E11
D10
E10
G12
F12
C8
A8
B8
C9
C14
D13
A10
B9
A13
B12
B13
B14
D14
E14
F13
G14
F15
G15
96
93
91
89
87
84
78
76
74
72
69
57
67
55
50
48
45
43
16
14
12
8
6
2
159
9
7
132
131
119
118
–
–
–
–
–
140
139
138
135
113
115
136
134
126
124
122
117
111
108
106
104
103
102
X5653
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
MC15-1
MC15-2
MC15-3
MC15-4
MC15-5
MC15-6
MC15-7
MC15-8
MC15-9
21
21
UIM
O
O
O/FCLK0
O/FCLK1
O/FCLK2
O
I/O/FI
I/O/FI
I/O/FI
MC14-1
MC14-2
MC14-3
MC14-4
MC14-5
MC14-6
MC14-7
MC14-8
MC14-9
21
21
O
O
O
O
O
O
I/O/FI
I/O/FI
I/O/FI
MC13-1
MC13-2
MC13-3
MC13-4
MC13-5
MC13-6
MC13-7
MC13-8
MC13-9
21
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
MC12-1
MC12-2
MC12-3
MC12-4
MC12-5
MC12-6
MC12-7
MC12-8
MC12-9
21
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
MC11-1
MC11-2
MC11-3
MC11-4
MC11-5
MC11-6
MC11-7
MC11-8
MC11-9
21
21
Figure 1. XC73144 Functional Block, Diagram
2-66
XC73144 CMOS EPLD
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
Parameter
Supply voltage with respect to GND
DC Input voltage with respect to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Value
-0.5 to 7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
-65 to +150
+260
Units
V
V
V
°
C
°
C
Warning
:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings condi-
tions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Symbol
V
CCINT
/
V
CCIO
V
CCIO
V
IL
V
IH
V
O
T
IN
Parameter
Supply voltage relative to GND
Supply voltage relative to GND
Supply voltage relative to GND
I/O supply voltage relative to GND
Low-level input voltage
High-level input voltage
Output voltage
Input signal transition time
Commercial
Industrial
Military
T
A
= 0
o
C to 70
o
C
T
A
= -40
o
C to 85
o
C
T
A
= -55
o
C to T
C
= +125
o
C
Min
4.75
4.5
4.5
3.0
0
2.0
0
Max
5.25
5.5
5.5
3.6
0.8
V
CC
+0.5
V
CCIO
50.0
Units
V
V
V
V
V
V
V
ns
Power Management
The XC73144 features a power-management scheme
which permits non-speed-critical paths of a design to be
operated at reduced power. Overall power dissipation is
often reduced significantly, since, in most systems only a
few paths are speed critical.
Macrocells can individually be specified for high per-
formance or low power operation by adding attributes to
the logic schematic, or declaration statements to the
behavioral description. To minimize power dissipation,
unused Function Blocks are turned off and unused
Macrocells in used Function Blocks are configured for low
power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) = MC
HP
(2.4) + MC
LP
(2.1) +
MC (0.015 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of Macrocells used
f
= Clock frequency (MHz)
Figure 2 shows a typical calculation for the XC73144 device,
programmed as eight 16-bit counters and operating at the
indicated clock frequency.
500
nce
r
400
Typical I
CC
(mA)
High
Pe
a
rform
300
P
Low
owe
200
100
0
50
Clock Frequency (MHz)
100
X5768
Figure 2. Typical I
CC
vs Frequency for XC73144
2-67
XC73144 CMOS EPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
5 V TTL High-level output voltage
V
OH
3.3 V High-level output voltage
5 V Low-level output voltage
V
OL
3.3 V Low-level output voltage
I
IL
I
OZ
C
IN
C
IN
C
OUT 1
I
CC1
2
Test Conditions
I
OH
= -4.0 mA
V
CC
= Min
I
OH
= -3.2 mA
V
CC
= Min
I
OL
= 24 mA (FO)
I
OL
= 12 mA (I/O)
V
CC
= Min
I
OL
= 10 mA
V
CC
= Min
V
CC
= Max
V
IN
= GND or V
CCIO
V
CC
= Max
V
O
= GND or V
CCIO
V
IN
= GND
f = 1.0 MHz
V
IN
= GND
f = 1.0 MHz
V
O
= GND
f = 1.0 MHz
V
IN
= V
CC
or GND
V
CCINT
= V
CCIO
= 5 V
f = 1.0 MHz @ 25
°
C
Min
2.4
2.4
Max
Units
V
V
0.5
0.4
±
10.0
±
10.0
8.0
12.0
20.0
250 Typ
V
V
µ
A
µ
A
pF
pF
pF
mA
Input leakage current
Output high-Z leakage current
Input capacitance for Input and I/O pins
Input capacitance for global control pins
(FCLK0, FCLK1, FCLK2, FOE0, FOE1)
Output capacitance
Supply Current (low power mode)
Notes: 1. Sample tested
2. Measured with device programmed as eight 16-bit counters
Power-up/Reset Timing Parameters
Symbol
t
WMR
t
RESET
Parameter
Master Reset input Low pulse width
Configuration completion time
Min
100
80
160
Typ
Max
Units
ns
µ
s
Slew Rate and Programmable Ground Control
Due to the large number of high current drivers available
on the XC73144, two programmable signal management
features have been included – slew rate control (SRC)
and ground control (GC). Slew rate control is primarily for
external system benefit, to reduce ringing and other cou-
pling phenomenon. SRC permits designers to select
either 1 V/ns or 1.5 V/ns slew rate on a pin-by-pin basis
for any output or I/O signal. This can be done with PLUS-
ASM or schematically, as needed. The defafult slew rate
is 1 V/ns. To assign the pins with equations (PLUSASM),
the designer needs to only declare them as follows:
FAST ON <signal name list>
This will assign the signals in the list to have a 1.5 V/ns
slew rate. Omitting the signal name list will globally set all
signals to be 1.5 V/ns. Specific signals therefore can be
declared with 1 V/ns slew rate as follows:
FAST OFF <signal name list>
Schematic control of SRC is also straightforward. Again,
the default is 1 V/ns, but to assign specific pins fast, the
designer need only attach the “FAST” attribute to the I/O
or output buffer or the corresponding pin.
Programmable ground control is useful for internal chip
signal management. The output buffers of the Fast Func-
tion Blocks have an impedance of around 7
Ω
when
switching high to low, where the High Density Function
Blocks impedance is around 14
Ω
. Since this low imped-
ance is negligible compared to the impedance of the pin
inductance when output current transients occur, a rea-
sonable ground connection can be made by driving
unused output pins low and physically attaching them to
external ground. The XC73144 architecture permits the
automatic assignment of external ground signals to all
Macrocells that are not declared as primary outputs or
I/Os. Note that the logical function of the buried Macrocell
is fully preserved, while its output driver is driving low and
physically attached to ground. Should designers not wish
to employ programmable ground control, they need only
declare all such pins as primary I/Os whether they will be
attached externally or not.
2-68
XC73144 CMOS EPLD
Fast Function Block (FFB) External AC Characteristics
3
XC73144-7
(Com Only)
XC73144-10 XC73144-12
XC73144-15
(Com Only)
(
Com/Ind Only)
Min
100.0
5.0
0
Max
Min
80.0
6.0
0
8.0
10.0
19.0
5.0
5.5
9.0
12.0
22.0
6.0
Max
Min
66.7
7.0
0
12.0
15.0
27.0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
Symbol Parameter
f
CF
t
SUF
t
HF
t
COF
t
PDFO
t
PDFU
t
CWF
Max count frequency
1, 2
Fast input setup time before FCLK
↑
1
Fast input hold time after FCLK
↑
FCLK
↑
to output valid
Fast input to output valid
1, 2
I/O to output valid
1, 2
Fast clock pulse width
Min
105.0
4.0
0
Max
5.5
7.5
13.5
4.0
High-Density Function Block (FB) External AC Characteristics
XC73144-7
(Com Only)
XC73144-10 XC73144-12
XC73144-15
(
Com Only) (Com/Ind Only
)
Min
62.5
16.0
0
Max
Min
55.6
18.0
0
10.0
6.0
0
7.0
0
20.0
25.0
5.0
6.0
5.5
7.5
23.0
30.0
6.0
8.5
12.0
9.0
0
28.0
36.0
Max
Min
45.5
22.0
0
15.0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
f
C
t
SU
t
H
t
CO
t
PSU
t
PH
t
PCO
t
PD
t
CW
t
PCW
Parameter
Max count frequency
1, 2
I/O setup time before FCLK
↑
1, 2
I/O hold time after FCLK
↑
FCLK
↑
to output valid
I/O setup time before p-term clock
↑
2
I/O hold time after p-term clock
↑
P-term clock
↑
to output valid
I/O to output valid
1, 2
Fast clock pulse width
P-term clock pulse width
Min
83.3
12.0
0
Max
7.0
4.0
0
15.0
18.0
4.0
5.0
Preliminary
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of t
FLOGILP
–
t
FLOGI
or t
LOGILP
– t
LOGI
.
2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
2-69
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