TC1272A
3-Pin Reset Monitor
Features
•
•
•
•
•
•
Precision V
DD
Monitor
140 msec Minimum RESET, Output Duration
Output Valid to V
DD
= 1.2V
V
DD
Transient Immunity
Small 3-Pin SOT-23B Package
No External Components
General Description
The TC1272A are cost-effective system supervisor
circuits designed to monitor V
DD
in digital systems and
provide a reset signal to the host processor, when
necessary. No external components are required.
The reset output is driven active within 65 µsec (typ.)
of V
DD
falling through the reset voltage threshold.
RESET is maintained active for a minimum of
140 msec after V
DD
rises above the reset threshold.
The TC1272A has a complimentary output. The output
of the TC1272A is valid down to V
DD
= 1.2V. The
device is available in a 3-Pin SOT-23B package.
The TC1272A device is optimized to reject fast
transient glitches on the V
DD
line.
Applications
•
•
•
•
Computers
Embedded Systems
Battery-Powered Equipment
Critical µP Power Supply Monitoring
Typical Application Circuit
V
DD
2
V
DD
RESET
1
V
DD
RESET
Input
Package Type
3-Pin SOT-23B*
RESET 1
TC1272A
GND
3
Processor
GND
V
DD
2
TC1272A
3 GND
Note:
3-Pin SOT-23B is equivalent to
JEDEC TO-236.
2004-2012 Microchip Technology Inc.
DS21877B-page 1
TC1272A
1.0
ELECTRICAL
CHARACTERISTICS
† Notice:
Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
Absolute Maximum Ratings†
Supply Voltage (V
DD
to GND) ..........................................6.0V
RESET .................................................. –0.3V to (V
DD
+0.3V)
Input Current, V
DD
.........................................................20 mA
Output Current, RESET ................................................20 mA
dV/dt (V
DD
) ............................................................. 100V/µsec
Operating Temperature Range..................... –40°C to +125°C
Power Dissipation (T
A
= 70°C):
3-Pin SOT-23B (derate 4 mW/°C above +70°C) ....320 mW
Storage Temperature Range ........................ –65°C to +150°C
Maximum Junction Temperature, T
J
.............................. 150°C
PIN FUNCTION TABLE
NAME
GND
RESET
Ground
RESET push-pull output remains
low while V
DD
is below the reset
voltage threshold and for 140 msec
(min.) after V
DD
rises above reset
threshold
FUNCTION
V
DD
ELECTRICAL CHARACTERISTICS
V
DD
= Full Range, T
A
= Operating Temperature Range, unless otherwise noted. Typical values are at T
A
= +25°C,
V
DD
= 5V for L/M/J, 3.3V for T/S, 3.0V for R and 2.5V for Z
(Note 1).
Parameter
V
DD
Range
Supply Current
Reset Threshold
(Note 2)
I
CC
V
TH
Sym
Min
1.0
1.2
—
—
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
Reset Threshold Tempco
V
DD
to Reset Delay,
Reset Active Time Out
Period
RESET Output Voltage
Low
V
OL
—
—
140
—
—
—
RESET Output Voltage
High
V
OH
0.8 V
DD
V
DD
– 1.5
Typ
—
—
12
9
4.63
—
4.38
—
4.00
—
3.08
—
2.93
—
2.63
—
2.32
—
30
65
320
—
—
—
—
—
Max
5.5
5.5
30
25
4.70
4.75
4.45
4.50
4.06
4.10
3.11
3.15
2.96
3.00
2.66
2.70
2.35
2.38
—
—
560
0.3
0.4
0.3
—
—
V
V
V
V
V
V
V
V
V
V
V
V
V
ppm/°C
µsec
msec
V
TC1272AR/S/T/Z:
V
DD
= V
TH
min, I
SINK
= 1.2 mA
TC1272AL/M/J:
V
DD
= V
TH
min, I
SINK
= 3.2 mA
V
DD
> 1.0V, I
SINK
= 50 µA
TC1272AR/S/T/Z:
V
DD
> V
TH
max,
I
SOURCE
= 500 µA
TC1272AL/M/J:
V
DD
> V
TH
max, I
SOURCE
= 800 µA
V
DD
= V
TH
to (V
TH
– 100 mV)
(Note 2)
TC1272AZ:
TC1272AR:
TC1272AS:
TC1272AT:
TC1272AJ:
TC1272AM:
V
µA
Units
V
Test Conditions
T
A
= 0°C to +70°C
T
A
= – 40°C to +125°C
TC1272AL/M/J:
TC1272AL:
V
DD
< 5.5V
T
A
= +25°C
T
A
= – 40°C to +125°C
T
A
= +25°C
T
A
= – 40°C to +125°C
T
A
= +25°C
T
A
= – 40°C to +125°C
T
A
= +25°C
T
A
= – 40°C to +125°C
T
A
= +25°C
T
A
= – 40°C to +125°C
T
A
= +25°C
T
A
= – 40°C to +125°C
T
A
= +25°C
T
A
= – 40°C to +125°C
TC1272AR/S/T/Z:
V
DD
< 3.6V
Note 1:
Production testing done at T
A
= +25°C, overtemperature limits ensured by QC screen.
2:
RESET Output for
TC1272A.
DS21877B-page 2
2004-2012 Microchip Technology Inc.
TC1272A
2.0
Note:
TYPICAL PERFORMANCE CHARACTERISTICS
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
18
TC1272A/R/S/T/Z, No Load
16
14
450
Power-up Reset Timeout (µsec)
120
V
DD
= 5V
400
350
300
250
200
150
100
50
Supply Current ( µA)
12
10
V
DD
= 3V
8
6
4
2
0
-40
-20
0
20
40
60
80
100
V
DD
= 1V
0
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
FIGURE 2-1:
Temperature.
16
Supply Current vs.
FIGURE 2-3:
vs. Temperature.
1.001
Power-up Reset Time Out
TC1272A/L/M/J, No Load
14
Supply Current ( µA)
12
10
Normalized Reset Threshold
V
DD
= 5V
1
V
DD
= 3V
8
6
4
2
0
-40
-20
0
20
40
60
80
100
120
0.999
V
DD
= 1V
0.998
0.997
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
FIGURE 2-2:
Temperature.
Supply Current vs.
FIGURE 2-4:
Normalized Reset
Threshold vs. Temperature.
2004-2012 Microchip Technology Inc.
DS21877B-page 3
TC1272A
3.0
3.1
APPLICATIONS INFORMATION
V
DD
Transient Rejection
Combinations above the curve are detected as a
brown-out or power-down condition. Transient immu-
nity can be improved by adding a capacitor in close
proximity to the V
DD
pin of the TC1272A.
The TC1272A provides accurate V
DD
monitoring and
reset timing during power-up, power-down and brown-
out/sag conditions. These devices also reject negative-
going transients (glitches) on the power supply line.
Figure 3-1 shows the maximum transient duration vs.
maximum negative excursion (overdrive) for glitch
rejection. Any combination of duration and overdrive
that lies under the curve will not generate a reset
signal.
V
DD
V
TH
Overdrive
3.2
RESET Signal Integrity During
Power-Down
Duration
Maximum Transient Duration (µsec)
400
T
A
= +25°C
320
240
160
TC1272A/L/M/J
The TC1272A RESET output is valid to V
DD
= 1.0V.
Below this voltage, the output becomes an "open cir-
cuit" and does not sink current. This means CMOS
logic inputs to the microcontroller will be floating at an
undetermined voltage. Most digital systems are com-
pletely shut down well above this voltage. However, in
situations where RESET must be maintained valid to
V
DD
= 0V, a pull-down resistor must be connected from
RESET to ground to discharge stray capacitances and
hold the output low (Figure 3-2). This resistor value,
though not critical, should be chosen such that it does
not appreciably load RESET under normal operation
(100 k will be suitable for most applications).
V
DD
V
DD
TC1272A
RESET
R
1
100 k
80
0
TC1272A/Z/R/S/T
GND
1
5
1000
100
Reset Comparator Overdrive
[V
TH
- V
DD
] (mv)
130
120
V
DD
to Reset Delay ( µsec)
FIGURE 3-2:
The addition of R
1
at the
RESET output of the TC1272A ensures that the
RESET output is valid to
V
DD
= 0V.
TC1272A/L/M/J
110
100
90
80
70
60
50
40
30
1
10
TC1272A/Z/R/S/T
100
1000
Reset Comparator Overdrive (mV)
[V
TH
- V
DD
] (mv)
FIGURE 3-1:
Maximum Transient
Duration vs. Overdrive for Glitch Rejection at
+25°C.
DS21877B-page 4
2004-2012 Microchip Technology Inc.
TC1272A
3.3
Controllers and Processors With
Bidirectional I/O Pins
Buffer
V
DD
TC1272A
4.7 k
RESET
GND
RESET
GND
PIC
®
Micro-
MCU
Buffered RESET
To Other System
Components
Some microcontrollers have bidirectional reset pins.
Depending on the current drive capability of the
controller pin, an indeterminate logic level may result if
there is a logic conflict. This can be avoided by adding
a 4.7 k resistor in series with the output of the
TC1272A (Figure 3-3). If there are other components in
the system that require a reset signal, they should be
buffered so as not to load the reset line. If the other
components are required to follow the reset I/O of the
microcontroller, the buffer should be connected as
shown with the solid line.
FIGURE 3-3:
Interfacing the TC1272A to
a Bidirectional RESET I/O.
2004-2012 Microchip Technology Inc.
DS21877B-page 5
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