74AHC30_09 datasheet, PDF - EEWORLD Datasheet

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74AHC30_09: DescriptionQuadruple 2-Input Positive-AND Gates 14-PDIP -40 to 85; File Size77KB，14 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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Quadruple 2-Input Positive-AND Gates 14-PDIP -40 to 85

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74AHC30; 74AHCT30

8-input NAND gate

Rev. 03 — 26 June 2009

Product data sheet

1. General description

The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC30; 74AHCT30 provides an 8-input NAND function.

2. Features

Balanced propagation delays

All inputs have Schmitt-trigger actions

Inputs accept voltages higher than V

Input levels:

For 74AHC30: CMOS level

For 74AHCT30: TTL level

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

74AHC30D

74AHCT30D

74AHC30PW

74AHCT30PW

74AHC30BQ

74AHCT30BQ

−40 °C

to +125

°C

DHVQFN14

−40 °C

to +125

°C

TSSOP14

−40 °C

to +125

°C

SO14

Description

plastic small outline package; 14 leads;

body width 3.9 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT108-1

SOT402-1

Type number

plastic dual in-line compatible thermal enhanced very SOT762-1

thin quad ﬂat package; no leads; 14 terminals;

body 2.5

0.85 mm

74AHC30_09 Related Products

	74AHC30_09	74AHCT30BQ	74AHC30BQ	74AHCT30
Description	Quadruple 2-Input Positive-AND Gates 14-PDIP -40 to 85	Quadruple 2-Input Positive-AND Gates 14-PDIP -40 to 85	Quadruple 2-Input Positive-AND Gates 14-PDIP -40 to 85	Quadruple 2-Input Positive-AND Gates 14-PDIP -40 to 85

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