Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9272
FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 0.75 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; V
IN
maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 80 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)
120 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP
FUNCTIONAL BLOCK DIAGRAM
DRVDD
AVDD1
AVDD2
PDWN
STBY
LOSW-A
LO-A
LI-A
LG-A
LOSW-B
LO-B
LI-B
LG-B
LOSW-C
LO-C
LI-C
LG-C
LOSW-D
LO-D
LI-D
LG-D
LOSW-E
LO-E
LI-E
LG-E
LOSW-F
LO-F
LI-F
LG-F
LOSW-G
LO-G
LI-G
LG-G
LOSW-H
LO-H
LI-H
LG-H
VGA
AAF
AD9272
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTA+
DOUTA–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTB+
DOUTB–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTC+
DOUTC–
LNA
12-BIT
ADC
SERIAL
LVDS
DOUTD+
DOUTD–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTE+
DOUTE–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTF+
DOUTF–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTG+
DOUTG–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
PORT
INTERFACE
SERIAL
LVDS
DATA
RATE
MULTIPLIER
DOUTH+
DOUTH–
FCO+
FCO–
DCO+
DCO–
REFERENCE
SWITCH
ARRAY
APPLICATIONS
GAIN+
GAIN–
CSB
SCLK
VREF
SDIO
CWD[7:0]+
AND
CWD[7:0]–
07029-001
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9272 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA), an antialiasing
filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 80 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 0.85 nV/√Hz at maximum
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 92 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
RBIAS
CLK+
CLK–
AD9272
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
Absolute Maximum Ratings.......................................................... 11
Thermal Impedance ................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 21
Ultrasound .................................................................................. 21
Channel Overview ..................................................................... 22
Input Overdrive .......................................................................... 25
CW Doppler Operation............................................................. 25
TGC Operation ........................................................................... 27
ADC ............................................................................................. 31
Clock Input Considerations ...................................................... 31
Serial Port Interface (SPI) .............................................................. 38
Hardware Interface..................................................................... 38
Memory Map .................................................................................. 40
Reading the Memory Map Table .............................................. 40
Reserved Locations .................................................................... 40
Default Values ............................................................................. 40
Logic Levels ................................................................................. 40
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
REVISION HISTORY
7/09—Rev. B to Rev. C
Changes to Input Overload Protection Section and Figure 43 ....... 25
Changes to Digital Outputs and Timing Section and Changes
to Figure 63 ...................................................................................... 33
Changes to Hardware Interface Section ...................................... 39
6/09—Rev. A to Rev. B
Changes to Product Highlights Section......................................... 3
Changes to Table 1 ............................................................................ 4
Changes to Absolute Maximum Ratings Table ........................... 11
Changes to Figure 22 ...................................................................... 17
Changes to Figure 33 and Figure 34 ............................................. 20
Changes to Low Noise Amplifier (LNA) Section ....................... 22
Changes to Active Impedance Matching Section ....................... 23
Changes to Figure 39 ...................................................................... 23
Changes to LNA Noise Section ..................................................... 24
Changes to Figure 47 ...................................................................... 28
Changes to Figure 48 and Figure 49 ............................................. 29
Changes to CSB Pin Section.......................................................... 36
Changes to Reading the Memory Map Table Section................ 40
4/09—Revision A: Initial Version
Rev. C | Page 2 of 44
AD9272
The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. There is also a standby
mode option that allows quick power-up for power cycling. In
CW Doppler operation, the VGA, antialiasing filter (AAF), and
ADC are powered down. The power of the time gain control
(TGC) path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom patterns, and custom user-defined test patterns
entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9272 is
available in a 16 mm × 16 mm, RoHS-compliant, 100-lead
TQFP. It is specified over the industrial temperature range of
−40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
Small Footprint. Eight channels are contained in a
small, space-saving package. A full TGC path, ADC, and
crosspoint switch are contained within a 100-lead, 16 mm ×
16 mm TQFP.
Low Power of 195 mW Per Channel at 40 MSPS.
Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
Ease of Use. A data clock output (DCO±) operates up to
480 MHz and supports double data rate (DDR) operation.
User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
Integrated Second-Order Antialiasing Filter. This filter is
placed between the VGA and the ADC and is programmable
from 8 MHz to 18 MHz.
2.
3.
4.
5.
6.
Rev. C | Page 3 of 44
AD9272
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
IN
= 5 MHz, R
S
= 50 Ω, LNA gain = 21.3 dB, LNA bias = high,
PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF cutoff = f
SAMPLE
/4.5, HPF = LPF cutoff/20.7 (default), full temperature, ANSI-644 LVDS mode,
unless otherwise noted.
Table 1.
Parameter
LNA CHARACTERISTICS
Gain
1
Conditions
Single-ended
input to
differential output
Single-ended
input to
single-ended
output
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
LNA output
limited to
4.4 V p-p
differential output
Min
AD9272-40
Typ
15.6/17.9/21.3
Max
Min
AD9272-65
Typ
15.6/17.9/21.3
Max
Min
AD9272-80
Typ
15.6/17.9/21.3
Max
Unit
dB
9.6/11.9/15.3
9.6/11.9/15.3
9.6/11.9/15.3
dB
Input Voltage Range
733/550/367
733/550/367
733/550/367
mV p-p
SE
2
Input Common
Mode
Input Resistance
0.9
R
FB
= 250 Ω
R
FB
= 500 Ω
R
FB
= ∞
LI-x
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
R
S
= 0 Ω,
R
FB
= ∞
R
FB
= ∞
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
GAIN+ = 0 V
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
R
S
= 50 Ω,
R
FB
= 200 Ω/
250 Ω/350 Ω
R
FB
= ∞
50
100
15
22
100
0.98/0.86/0.75
0.9
50
100
15
22
100
0.98/0.86/0.75
0.9
50
100
15
22
100
0.98/0.86/0.75
V
Ω
Ω
kΩ
pF
MHz
nV/√Hz
Input Capacitance
−3 dB Bandwidth
Input-Referred
Noise Voltage
Input Noise Current
1 dB Input Com-
pression Point
1
1.0/0.8/0.5
1
1.0/0.8/0.5
1
1.0/0.8/0.5
pA/√Hz
mV p-p
Noise Figure
Active Termination
Matched
Unterminated
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Filter
Cutoff -In Range
AAF Low-Pass Filter
Cutoff - Out of
Range
3
AAF Bandwidth
Tolerance -In
Range
4.8/4.1/3.2
4.8/4.1/3.2
4.8/4.0/3.2
dB
3.4/2.8/2.3
3.4/2.8/2.3
3.4/2.8/2.3
dB
−3 dB,
programmable
−3 dB,
programmable,
AAF Bandwidth
Tolerance
8 to 18
5 to 8 and
18 to 35
8 to 18
5 to 8 and
18 to 35
8 to 18
5 to 8 and
18 to 35
MHz
MHz
±10
±10
±10
%
Rev. C | Page 4 of 44
AD9272
Parameter
Group Delay
Variation
1
Input-Referred
Noise Voltage
Noise Figure
Conditions
f = 1 MHz to
18 MHz,
GAIN+ = 0 V to
1.6 V
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
R
FB
= ∞
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
R
S
= 50 Ω,
R
FB
= 200 Ω/
250 Ω/350 Ω
R
FB
= ∞
No signal,
correlated/
uncorrelated
Min
AD9272-40
Typ
±2
Max
Min
AD9272-65
Typ
±2
Max
Min
AD9272-80
Typ
±2
Max
Unit
ns
1.26/1.04/0.85
1.26/1.04/0.85
1.26/1.04/0.85
nV/√Hz
Active Termina-
tion Matched
Unterminated
Correlated Noise
Ratio
Output Offset
Signal-to-Noise
Ratio (SNR)
8.0/6.6/4.7
7.7/6.2/4.5
7.6/6.1/4.4
dB
4.7/3.7/2.8
−30
4.6/3.6/2.8
−30
4.5/3.6/2.7
−30
dB
dB
−35
f
IN
= 5 MHz at
−10 dBFS, GAIN+
=0V
f
IN
= 5 MHz at
−1 dBFS, GAIN+ =
1.6 V
f
IN
= 5 MHz at
−10 dBFS, GAIN+
=0V
f
IN
= 5 MHz at
−1 dBFS, GAIN+ =
1.6 V
f
IN
= 5 MHz at
−10 dBFS, GAIN+
=0V
f
IN
= 5 MHz at
−1 dBFS, GAIN+ =
1.6 V
f
IN1
= 5.0 MHz at
−1 dBFS,
f
IN2
= 5.01 MHz at
−21 dBFS, GAIN+
= 1.6 V,
LNA gain = 21.3 dB
f
IN1
= 5.0 MHz at −1
dBFS
Overrange
condition
4
Full TGC path,
f
IN
= 5 MHz,
GAIN+ = 0 V to
1.6 V
Differential input
to differential
output
65
+35
−35
64
+35
−35
63
+35
LSB
dBFS
57
56
54.5
dBFS
Harmonic Distortion
Second
Harmonic
−62
−58
−55
dBc
−60
−61
−58
dBc
Third Harmonic
−71
−60
−60
dBc
−57
−55
−56
dBc
Two-Tone IMD3
(2 × F1 − F2)
Distortion
−75
−75
−75
dBc
Channel-to-Channel
Crosstalk
−70
−65
0.3
−70
−65
0.3
−70
−65
0.3
dB
dB
Degrees
Channel-to-Channel
Delay Variation
PGA GAIN
21/24/27/30
21/24/27/30
21/24/27/30
dB
Rev. C | Page 5 of 44
京公网安备 11010802033920号
EEWORLD
