AD9272_09 datasheet, PDF - EEWORLD Datasheet

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AD9272_09: DescriptionOctal LNA/VGA/AAF/ADC and Crosspoint Switch; File Size731KB，44 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Octal LNA/VGA/AAF/ADC and Crosspoint Switch

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Octal LNA/VGA/AAF/ADC

and Crosspoint Switch

AD9272

FEATURES

8 channels of LNA, VGA, AAF, and ADC

Low noise preamplifier (LNA)

Input-referred noise voltage = 0.75 nV/√Hz

(gain = 21.3 dB) @ 5 MHz typical

SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB

Single-ended input; V

maximum = 733 mV p-p/

550 mV p-p/367 mV p-p

Dual-mode active input impedance matching

Bandwidth (BW) > 100 MHz

Full-scale (FS) output = 4.4 V p-p differential

Variable gain amplifier (VGA)

Attenuator range = −42 dB to 0 dB

SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB

Linear-in-dB gain control

Antialiasing filter (AAF)

Programmable 2nd-order low-pass filter (LPF) from

8 MHz to 18 MHz

Programmable high-pass filter (HPF)

Analog-to-digital converter (ADC)

12 bits at 10 MSPS to 80 MSPS

SNR = 70 dB

SFDR = 75 dB

Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)

Data and frame clock outputs

Includes an 8 × 8 differential crosspoint switch to support

continuous wave (CW) Doppler

Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)

120 mW per channel in CW Doppler

Flexible power-down modes

Overload recovery in <10 ns

Fast recovery from low power standby mode, <2 μs

100-lead TQFP

FUNCTIONAL BLOCK DIAGRAM

DRVDD

AVDD1

AVDD2

PDWN

STBY

LOSW-A

LO-A

LI-A

LG-A

LOSW-B

LO-B

LI-B

LG-B

LOSW-C

LO-C

LI-C

LG-C

LOSW-D

LO-D

LI-D

LG-D

LOSW-E

LO-E

LI-E

LG-E

LOSW-F

LO-F

LI-F

LG-F

LOSW-G

LO-G

LI-G

LG-G

LOSW-H

LO-H

LI-H

LG-H

VGA

AAF

AD9272

LNA

VGA

AAF

12-BIT

ADC

SERIAL

LVDS

DOUTA+

DOUTA–

LNA

VGA

AAF

12-BIT

ADC

SERIAL

LVDS

DOUTB+

DOUTB–

LNA

VGA

AAF

12-BIT

ADC

SERIAL

LVDS

DOUTC+

DOUTC–

LNA

12-BIT

ADC

SERIAL

LVDS

DOUTD+

DOUTD–

LNA

VGA

AAF

12-BIT

ADC

SERIAL

LVDS

DOUTE+

DOUTE–

LNA

VGA

AAF

12-BIT

ADC

SERIAL

LVDS

DOUTF+

DOUTF–

LNA

VGA

AAF

12-BIT

ADC

SERIAL

LVDS

DOUTG+

DOUTG–

LNA

VGA

AAF

12-BIT

ADC

SERIAL

PORT

INTERFACE

SERIAL

LVDS

DATA

RATE

MULTIPLIER

DOUTH+

DOUTH–

FCO+

FCO–

DCO+

DCO–

REFERENCE

SWITCH

ARRAY

APPLICATIONS

GAIN+

GAIN–

CSB

SCLK

VREF

SDIO

CWD[7:0]+

AND

CWD[7:0]–

07029-001

Medical imaging/ultrasound

Automotive radar

GENERAL DESCRIPTION

The AD9272 is designed for low cost, low power, small size, and

ease of use. It contains eight channels of a low noise preamplifier

(LNA) with a variable gain amplifier (VGA), an antialiasing

filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-

digital converter (ADC).

Each channel features a variable gain range of 42 dB, a fully

differential signal path, an active input preamplifier termination, a

maximum gain of up to 52 dB, and an ADC with a conversion

rate of up to 80 MSPS. The channel is optimized for dynamic

performance and low power in applications where a small

package size is critical.

Figure 1.

The LNA has a single-ended-to-differential gain that is selectable

through the SPI. The LNA input-referred noise voltage is typically

0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred

noise voltage of the entire channel is 0.85 nV/√Hz at maximum

gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB

LNA gain, the input SNR is about 92 dB. In CW Doppler mode,

the LNA output drives a transconductance amp that is switched

through an 8 × 8 differential crosspoint switch. The switch is

programmable through the SPI.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

RBIAS

CLK+

CLK–

AD9272

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 8

Switching Specifications .............................................................. 9

Absolute Maximum Ratings.......................................................... 11

Thermal Impedance ................................................................... 11

ESD Caution ................................................................................ 11

Pin Configuration and Function Descriptions ........................... 12

Typical Performance Characteristics ........................................... 15

Equivalent Circuits ......................................................................... 19

Theory of Operation ...................................................................... 21

Ultrasound .................................................................................. 21

Channel Overview ..................................................................... 22

Input Overdrive .......................................................................... 25

CW Doppler Operation............................................................. 25

TGC Operation ........................................................................... 27

ADC ............................................................................................. 31

Clock Input Considerations ...................................................... 31

Serial Port Interface (SPI) .............................................................. 38

Hardware Interface..................................................................... 38

Memory Map .................................................................................. 40

Reading the Memory Map Table .............................................. 40

Reserved Locations .................................................................... 40

Default Values ............................................................................. 40

Logic Levels ................................................................................. 40

Outline Dimensions ....................................................................... 44

Ordering Guide .......................................................................... 44

REVISION HISTORY

7/09—Rev. B to Rev. C

Changes to Input Overload Protection Section and Figure 43 ....... 25

Changes to Digital Outputs and Timing Section and Changes

to Figure 63 ...................................................................................... 33

Changes to Hardware Interface Section ...................................... 39

6/09—Rev. A to Rev. B

Changes to Product Highlights Section......................................... 3

Changes to Table 1 ............................................................................ 4

Changes to Absolute Maximum Ratings Table ........................... 11

Changes to Figure 22 ...................................................................... 17

Changes to Figure 33 and Figure 34 ............................................. 20

Changes to Low Noise Amplifier (LNA) Section ....................... 22

Changes to Active Impedance Matching Section ....................... 23

Changes to Figure 39 ...................................................................... 23

Changes to LNA Noise Section ..................................................... 24

Changes to Figure 47 ...................................................................... 28

Changes to Figure 48 and Figure 49 ............................................. 29

Changes to CSB Pin Section.......................................................... 36

Changes to Reading the Memory Map Table Section................ 40

4/09—Revision A: Initial Version

Rev. C | Page 2 of 44

AD9272_09 Related Products

	AD9272_09	AD9272-65EBZ1	AD9272-80KITZ1	AD9272BSVZ-401	AD9272BSVZRL-401	AD9272BSVZRL-651	AD9272BSVZ-651	AD9272BSVZ-801	AD9272BSVZRL-801
Description	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch	Octal LNA/VGA/AAF/ADC and Crosspoint Switch

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