Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4
V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels, T
A
= 25°C.
5
Guaranteed by design. Sample tested to ensure compliance.
6
V
DD
= 3 V; P = 16; RF
IN
= 900 MHz; IF
IN
= 540 MHz, T
A
= 25°C.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See
TPC 16.
8
The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
Same conditions as listed in Note 10.
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; Offset frequency = 1 kHz; f
RF
= 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Specifications subject to change without notice.
REV. A
–3–
ADF4210/ADF4211/ADF4212/ADF4213
(V 1 = V 2 = 3 V 10%, 5 V
TIMING CHARACTERISTICS
= AGND = DGND = 0 V; T = T
DD
DD
IF
IF
A
10%; V
DD
1, V
DD
2
≤
V
P
1, V
P
2
≤
6 V
MIN
to T
MAX
unless otherwise noted.)
10%; AGND
RF
= DGND
RF
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Set-Up Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Set-Up Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.
t
3
CLOCK
t
4
t
1
DATA
DB20
(MSB)
DB19
t
2
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B,
IF
IN
A, IF
IN
B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
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