a
Dual RF/IF PLL Frequency Synthesizers
ADF4210/ADF4211/ADF4212/ADF4213
GENERAL DESCRIPTION
FEATURES
ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V
P
) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode
The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B Counters
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(12-bit) counters, in conjunction with the dual modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
APPLICATIONS
The devices operate with a power supply ranging from 2.7 V to
Base Stations for Wireless Radio (GSM, PCS, DCS,
5 V and can be powered down when not in use.
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
V
DD
1
V
DD
2
V
P
1
V
P
2
R
SET
12-BIT IF
B-COUNTER
IF
IN
IF
PRESCALER
8-BIT IF
A-COUNTER
PHASE
COMPARATOR
REFERENCE
CHARGE
PUMP
IF CURRENT
SETTING
IFCP3 IFCP2 IFCP1
CP
IF
REF
IN
OSCILLATOR
14-BIT IF
R-COUNTER
IF
LOCK
DETECT
CLOCK
DATA
LE
24-BIT
DATA
SDOUT
REGISTER
14-BIT RF
R-COUNTER
OUTPUT
MUX
MUXOUT
RFCP3 RFCP2 RFCP1
RF
LOCK
DETECT
IF CURRENT
SETTING
CHARGE
PUMP
PHASE
COMPARATOR
REFERENCE
R
SET
FL
O
SWITCH
FL
O
12-BIT RF
B-COUNTER
RF
IN
RF
PRESCALER
6-BIT RF
A-COUNTER
CP
RF
ADF4210/ADF4211/
ADF4212/ADF4213
AGND
IF
DGND
RF
AGND
RF
DGND
IF
DGND
IF
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
DD
1, V
DD
2
≤
V
P
1, V
P
2
≤
6.0 V ; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; R
SET
= 2.7 k
T
A
= T
MIN
to T
MAX
unless otherwise noted.)
P
arameter
RF/IF CHARACTERISTICS (3 V)
RF Input Frequency (RF
IN
)
ADF4210
ADF4211
ADF4212
ADF4213
RF Input Sensitivity
IF Input Frequency (IF
IN
)
ADF4210
ADF4211
ADF4212
ADF4213
IF Input Sensitivity
Maximum Allowable
Prescaler Output Frequency
3
RF/IF CHARACTERISTICS (5 V)
RF Input Frequency (RF
IN
)
ADF4210
ADF4211
ADF4212
ADF4213
RF Input Sensitivity
IF Input Frequency (IF
IN
)
ADF4210
ADF4211
ADF4212
ADF4213
IF Input Sensitivity
Maximum Allowable
Prescaler Output Frequency
3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
5
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
B Version
B Chips
2
Unit
1
dBm to 50
;
Test Conditions/Comments
See Figure 3 for Input Circuit.
Use a square wave for frequencies lower than F
MIN
.
0.1/1.2
0.1/2.0
0.15/2.7
0.2/3.0
–10/0
60/550
60/550
0.06/1.0
0.06/1.0
–10/0
165
0.1/1.2
0.1/2.0
0.15/2.7
0.2/3.0
–10/0
60/550
60/550
0.06/1.0
0.06/1.0
–10/0
165
GHz min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz min/max
MHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
0.18/1.2
0.18/2.0
0.2/2.3
0.2/2.5
–5/0
100/550
100/550
0.1/1.0
0.1/1.0
–5/0
200
0/115
–5/0
10
±
100
55
0.18/1.2
0.18/2.0
0.2/2.3
0.2/2.5
–5/0
100/550
100/550
0.1/1.0
0.1/1.0
–5/0
200
0/115
–5/0
10
±
100
55
GHz min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz min/max
MHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
MHz min/max
dBm min/max
pF max
µA
max
MHz max
See Figure 3 for Input Circuit.
Use a square wave for frequencies lower than F
MIN
.
See Figure 2 for Input Circuit.
For F < 5 MHz, use dc-coupled square wave
(0 to V
DD
).
AC-Coupled. When dc-coupled, 0 to V
DD
max
(CMOS-Compatible)
5
625
3
1.5/5.6
1
2
2
2
0.8
×
DV
DD
0.2
×
DV
DD
±
1
10
DV
DD
– 0.4
0.4
5
625
3
1.5/5.6
1
2
2
2
0.8
×
DV
DD
0.2
×
DV
DD
±
1
10
DV
DD
– 0.4
0.4
mA typ
µA
typ
% typ
kΩ, min/max
nA typ
% typ
% typ
% typ
V min
V max
µA
max
pF max
V min
V max
Programmable: See Table V
With R
SET
= 2.7 kΩ
With R
SET
= 2.7 kΩ
0.5 V V
CP
0.5 V V
CP
V
CP
= V
P
/2
V
P
– 0.5 V
V
P
– 0.5 V
I
OH
= 500
µA
I
OL
= 500
µA
–2–
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
Parameter
POWER SUPPLIES
V
DD
1
V
DD
2
V
P
I
DD
(RF + IF)
6
ADF4210
ADF4211
ADF4212
ADF4213
I
DD
(RF Only)
ADF4210
ADF4211
ADF4212
ADF4213
I
DD
(IF Only)
ADF4210
ADF4211
ADF4212
ADF4213
I
P
(I
P
1 + I
P
2)
Low-Power Sleep Mode
NOISE CHARACTERISTICS
ADF4213 Phase Noise Floor
7
Phase Noise Performance
8
ADF4210/ADF4211, IF: 540 MHz Output
9
ADF4212/ADF4213, IF: 900 MHz Output
10
ADF4210/ADF4211, RF: 900 MHz Output
10
ADF4212/ADF4213, RF: 900 MHz Output
10
ADF4211/ADF4212, RF: 1750 MHz Output
12
ADF4211/ADF4212, RF: 1750 MHz Output
13
ADF4212/ADF4213, RF: 2400 MHz Output
14
Spurious Signals
ADF4210/ADF4211, IF: 540 MHz Output
9
ADF4212/ADF4213, IF: 900 MHz Output
10
ADF4210/ADF4211, RF: 900 MHz Output
10
ADF4212/ADF4213, RF: 900 MHz Output
10
ADF4211/ADF4212, RF: 1750 MHz Output
12
ADF4211/ADF4212, RF: 1750 MHz Output
13
ADF4212/ADF4213, RF: 2400 MHz Output
14
B Version B Chips
2
Unit
2.7/5.5
V
DD
1
V
DD
1/6.0
11.5
15.0
17.5
20
6.75
10
12.5
15
5.5
5.5
5.5
5.5
1.0
1
–171
–164
–91
–89
–89
–91
–85
–67
–88
–88/–90
–90/–94
–90/–94
–90/–94
–80/–82
–65/–70
–80/–82
2.7/5.5
V
DD
1
V
DD
1/6.0
11.5
15.0
17.5
20
6.75
10
12.5
15
5.5
5.5
5.5
5.5
1.0
1
–171
–164
–91
–89
–89
–91
–85
–67
–88
–88/–90
–90/–94
–90/–94
–90/–94
–80/–82
–65/–70
–80/–82
V min/V max
V min/V max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
µA
typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
Test Conditions/Comments
V
DD
1, V
DD
2
V
DD
1, V
DD
2
6.0 V
9.0 mA typical
11.0 mA typical
13.0 mA typical
15 mA typical
5.0 mA typical
7.0 mA typical
9.0 mA typical
11 mA typical
4.5 mA typical
4.5 mA typical
4.5 mA typical
4.5 mA typical
T
A
= 25°C, 0.55 mA typical
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
See Note 11
See Note 11
See Note 11
See Note 11
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 1 MHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
See Note 11
See Note 11
See Note 11
See Note 11
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4
V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels, T
A
= 25°C.
5
Guaranteed by design. Sample tested to ensure compliance.
6
V
DD
= 3 V; P = 16; RF
IN
= 900 MHz; IF
IN
= 540 MHz, T
A
= 25°C.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See
TPC 16.
8
The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
Same conditions as listed in Note 10.
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; Offset frequency = 1 kHz; f
RF
= 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Specifications subject to change without notice.
REV. A
–3–
ADF4210/ADF4211/ADF4212/ADF4213
(V 1 = V 2 = 3 V 10%, 5 V
TIMING CHARACTERISTICS
= AGND = DGND = 0 V; T = T
DD
DD
IF
IF
A
10%; V
DD
1, V
DD
2
≤
V
P
1, V
P
2
≤
6 V
MIN
to T
MAX
unless otherwise noted.)
10%; AGND
RF
= DGND
RF
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Set-Up Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Set-Up Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.
t
3
CLOCK
t
4
t
1
DATA
DB20
(MSB)
DB19
t
2
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B,
IF
IN
A, IF
IN
B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP
θ
JA
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP
θ
JA
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W
CSP
θ
JA
(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
WARNING!
ESD SENSITIVE DEVICE
Model
ADF4210BRU
ADF4210BCP
ADF4211BRU
ADF4211BCP
ADF4212BRU
ADF4212BCP
ADF4213BRU
ADF4213BCP
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
–4–
Package Option*
RU-20
CP-20
RU-20
CP-20
RU-20
CP-20
RU-20
CP-20
REV. A
*Contact
the factory for chip availability.
ADF4210/ADF4211/ADF4212/ADF4213
PIN FUNCTION DESCRIPTIONS
Pin Number
TSSOP
1
Mnemonic
V
DD
1
Function
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as
close as possible to this pin. V
DD
1 should have a value of between 2.7 V and 5.5 V. V
DD
1 must have
the same potential as V
DD
2.
Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
1. In systems where
V
DD
1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry.
RF/IF Fastlock Mode.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.
Digital Ground for the IF Digital, Interface and Control Circuitry.
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled
Reference Frequency to be accessed externally.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
13.5
I
CP MAX
=
R
SET
So, with
R
SET
= 2.7 kΩ,
I
CP MAX
= 5 mA for both the RF and IF Charge Pumps.
Ground Pin for the IF Analog Circuitry.
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry.
Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
2. In systems where
V
DD
2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. V
DD
2 should have a value of between 2.7 V and 5.5 V. V
DD
2
must have the same potential as V
DD
1.
2
3
4
5
6
7
8
9
10
11
V
P
1
CP
RF
DGND
RF
RF
IN
AGND
RF
FL
O
REF
IN
DGND
IF
MUXOUT
CLK
12
13
14
DATA
LE
R
SET
15
16
17
18
19
20
AGND
IF
IF
IN
DGND
IF
CP
IF
V
P
2
V
DD
2
PIN CONFIGURATIONS
TSSOP
V
P
1
CP-20
V
DD
1
V
DD
2
CP
IF
16
15
DGND
IF
14
IF
IN
13
AGND
IF
12
R
SET
11
LE
V
DD
1
1
V
P
1
2
CP
RF 3
DGND
RF 4
RF
IN 5
AGND
RF 6
20
V
DD
2
20
19
18 17
ADF4210/
ADF4211/
ADF4212/
ADF4213
19
V 2
P
18
CP
IF
17
DGND
IF
16
IF
IN
CP
RF 1
DGND
RF 2
RF
IN 3
AGND
RF
FL
O
4
5
ADF4210/
ADF4211/
ADF4212/
ADF4213
TOP VIEW
(Not to Scale)
6
7
8
9
10
TOP VIEW
15
AGND
IF
(Not to Scale)
14
R
SET
FL
O 7
13
LE
12
DATA
11
CLK
REF
IN 8
DGND
IF 9
MUXOUT
10
REF
IN
CLK
V
P
2
DGND
IF
REV. A
–5–
MUXOUT
DATA
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