CAT24C32
32-Kb I
2
C CMOS Serial
EEPROM
Description
The CAT24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I
2
C protocol.
External address pins make it possible to address up to eight
CAT24C32 devices on the same bus.
Features
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Supports Standard, Fast and Fast−Plus I
2
C Protocol
1.7 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
PDIP, SOIC, TSSOP, TDFN, UDFN 8−lead Packages and TSOP
5−lead Package
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SOIC−8
W SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8
VP2 SUFFIX
CASE 511AK
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
UDFN−8
HU3 SUFFIX
CASE 517AX
TSOP−5
TS SUFFIX
CASE 483
PIN CONFIGURATIONS
1
SCL
V
SS
SDA
TSOP−5 (TS)
A
0
A
1
A
2
V
SS
1
V
CC
WP
SCL
SDA
V
CC
WP
PDIP (L), SOIC (W), TSSOP (Y),
TDFN (VP2), UDFN (HU3, HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
August, 2012
−
Rev. 15
1
Publication Order Number:
CAT24C32/D
CAT24C32
DEVICE MARKINGS
(PDIP−8)
(SOIC−8)
24C32F
AXXX
YYWWG
24C32F
AYMXXX
24C32F
A
XXX
YY
WW
G
= Specific Device Code
= Assembly Location
= Last Three Digits of Assembly Lot Number
= Production Year (Last Two Digits)
= Production Week (Two Digits)
= Pd−Free designator
(TSOP−5)
24C32F
A
Y
M
XXX
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
C5 MG
G
(TSSOP−8)
C5 = CAT24C32
M = Date Code
G
= Pb−Free Package
(UDFN−8 and TDFN−8)
BBB
AXX
YM
C32F
AYMXXX
C32F
A
Y
M
XXX
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
BBB
BBB
BBB
A
XX
Y
M
= C5U = CAT24C32HU4
= C5V = CAT24C32HU3
= C5T = CAT24C32VP2
= Assembly Location
= Last Two Digits of Assembly Lot Number
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
V
CC
PIN FUNCTION
SCL
CAT24C32
SDA
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
V
SS
Function
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
A
2
, A
1
, A
0
WP
Figure 1. Functional Symbol
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CAT24C32
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(
V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +125°C and V
CC
= 1.7 V to 5.5 V, T
A
=
−20°C
to +85°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
Parameter
Read Current
Write Current
Standby Current
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
T
A
=
−40°C
to +85°C
V
CC
≤
3.3 V
T
A
=
−40°C
to +85°C
V
CC
> 3.3 V
T
A
=
−40°C
to +125°C
I
L
V
IL
V
IH
V
OL1
V
OL2
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
< 2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Pin at GND or V
CC
−0.5
V
CC
x 0.7
Min
Max
1
2
1
3
5
2
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
mA
V
V
V
V
Units
mA
mA
mA
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +125°C and V
CC
= 1.7 V to 5.5 V, T
A
=
−20°C
to +85°C, unless otherwise specified.)
Symbol
C
IN
(Note 4)
C
IN
(Note 4)
I
WP
(Note 5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0 V, T
A
= 25°C, f = 1.0 MHz
V
IN
= 0 V, T
A
= 25°C, f = 1.0 MHz
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.7 V
V
IN
> V
IH
I
A
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.7 V
V
IN
> V
IH
Max
8
6
130
120
80
2
50
35
25
2
mA
Units
pF
pF
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
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CAT24C32
Table 5. A.C. CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +125°C and V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C.) (Note 6)
Standard
V
CC
= 1.7 V
−
5.5 V
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 7)
t
F
(Note 7)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 7)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 7, 8)
6.
7.
8.
9.
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP
and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and
SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
0.1
4
4.7
3.5
100
100
0
1
5
1
4
4.7
4
4.7
0
250
1,000
300
0.6
1.3
0.9
50
100
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
0.25
0.5
0.40
Fast
V
CC
= 1.7 V
−
5.5 V
Min
Max
400
0.25
0.45
0.40
0.25
0
50
100
100
Fast−Plus
(Note 9)
V
CC
= 2.5 V
−
5.5 V
T
A
=
−405C
to +855C
Min
Max
1,000
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Fast−Plus (1 MHz) speed class available for product revision “F”. The die revision “F” is identified by letter “F” or a dedicated marking code
on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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CAT24C32
Power−On Reset (POR)
Each CAT24C32 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after V
CC
exceeds the POR trigger level and will
power down into Reset mode when V
CC
drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL:
The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA:
The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A
0
, A
1
and A
2
:
The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard−wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally.
WP:
When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally.
Functional Description
The CAT24C32 supports the Inter−Integrated Circuit
2
C) Bus protocol. The protocol relies on the use of a Master
(I
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C32
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
The 2−wire I
2
C bus consists of two lines, SCL and SDA,
connected to the V
CC
supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
I
2
C Bus Protocol
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAT24C32, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A
2
, A
1
and A
0
, must match
the logic state of the similarly named input pins. The R/W
bit tells the Slave whether the Master intends to read (1) or
write (0) data (Figure 3).
Acknowledge
During the 9
th
clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
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