SN74LS192
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT
BINARY UP/DOWN
COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter
and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary
Counter. Separate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously. The outputs
change state synchronous with the LOW-to-HIGH transitions on the
clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without
extra logic, thus simplifying multistage counter designs. Individual
preset inputs allow the circuits to be used as programmable counters.
Both the Parallel Load (PL) and the Master Reset (MR) inputs
asynchronously override the clocks.
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PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
LOW POWER SCHOTTKY
•
•
•
•
•
•
Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
P
0
15
MR
14
TC
D
13
TC
U
12
PL
11
P
2
10
P
3
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as the Dual
In-Line Package.
16
J SUFFIX
CERAMIC
CASE 620-09
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1
P
1
2
Q
1
3
Q
0
4
CP
D
5
CP
U
6
Q
2
7
Q
3
8
GND
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
LOGIC SYMBOL
PIN NAMES
11
15
1
10
9
CP
U
CP
D
MR
PL
P
n
Q
n
TC
D
TC
U
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
5
4
CP
U
CP
D
PL
P
0
P
1
P
2
P
3
TC
U
12
13
MR Q
0
Q
1
Q
2
Q
3
14
3
2
6
7
TC
D
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
μA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
©
Semiconductor Components Industries, LLC, 2006
V
CC
= PIN 16
GND = PIN 8
July, 2006
−
Rev. 7
1
Publication Order Number:
SN74LS192/D
SN74LS192
LOGIC DIAGRAMS (continued)
P
0
P
1
P
2
P
3
P
L
(LOAD)
CP
U
(UP COUNT)
11
5
15
1
10
9
12
TC
U
(CARRY
OUTPUT)
S
D
T
Q
T
S
D
Q
T
S
D
Q
T
S
D
Q
C
D
Q
C
D
Q
C
D
Q
C
D
Q
13
CP
D
(DOWN
COUNT)
MR
(CLEAR)
4
14
3
2
6
7
TC
D
(BORROW
OUTPUT)
Q
0
Q
1
Q
2
Q
3
LS193
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS192 and LS193 are Asynchronously Presettable
Decade and 4-Bit Binary Synchronous UP / DOWN
(Reversable) Counters. The operating modes of the LS192
decade counter and the LS193 binary counter are identical,
with the only difference being the count sequences as noted
in the State Diagrams. Each circuit contains four
master/slave flip-flops, with internal gating and steering logic
to provide master reset, individual preset, count up and count
down operations.
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes the
slave, and thus the Q output to change state. Synchronous
switching, as opposed to ripple counting, is achieved by
driving the steering gates of all stages from a common Count
Up line and a common Count Down line, thereby causing all
state changes to be initiated simultaneously. A
LOW-to-HIGH transition on the Count Up input will advance
the count by one; a similar transition on the Count Down input
will decrease the count by one. While counting with one clock
input, the other should be held HIGH. Otherwise, the circuit
will either count by twos or not at all, depending on the state of
the first flip-flop, which cannot toggle as long as either Clock
input is LOW.
The Terminal Count Up (TC
U
) and Terminal Count Down
(TC
D
) outputs are normally HIGH. When a circuit has
reached the maximum count state (9 for the LS192, 15 for the
LS193), the next HIGH-to-LOW transition of the Count Up
Clock will cause TC
U
to go LOW. TC
U
will stay LOW until CP
U
goes HIGH again, thus effectively repeating the Count Up
Clock, but delayed by two gate delays. Similarly, the TC
D
output will go LOW when the circuit is in the zero state and the
Count Down Clock goes LOW. Since the TC outputs repeat
the clock waveforms, they can be used as the clock input
signals to the next higher order circuit in a multistage counter.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, information
present on the Parallel Data inputs (P
0
, P
3
) is loaded into the
counter and appears on the outputs regardless of the
conditions of the clock inputs. A HIGH signal on the Master
Reset input will disable the preset gates, override both Clock
inputs, and latch each Q output in the LOW state. If one of the
Clock inputs is LOW during and after a reset or load
operation, the next LOW-to-HIGH transition of that Clock will
be interpreted as a legitimate signal and will be counted.
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3
SN74LS192
MODE SELECT TABLE
MR
H
L
L
L
L
PL
X
L
H
H
H
CP
U
X
X
H
H
CP
D
X
X
H
H
MODE
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
= LOW-to-HIGH Clock Transition
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
−55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
−0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
54, 74
74
2.5
2.7
54
74
−0.65
3.5
3.5
0.25
0.35
0.4
0.5
20
0.1
−0.4
−20
−100
34
Min
2.0
0.7
0.8
−1.5
Typ
Max
Unit
V
V
V
V
V
V
V
μA
mA
mA
mA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
=
−
18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
OL
Output LOW Voltage
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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4
SN74LS192
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
CP
U
Input to
TC
U
Output
CP
D
Input to
TC
D
Output
Clock to Q
PL to Q
Parameter
Maximum Clock Frequency
Min
25
Typ
32
17
18
16
15
27
30
24
25
23
Limits
Symbol
t
W
t
s
t
h
t
rec
Parameter
Any Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Min
20
20
5.0
40
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5.0 V
Test Conditions
26
24
24
24
38
47
40
40
35
Max
Unit
MHz
ns
ns
ns
ns
ns
Test Conditions
V
CC
= 5.0 V
C
L
= 15 pF
MR Input to Any Output
AC SETUP REQUIREMENTS
(T
A
= 25°C)
DEFINITIONS OF TERMS
SETUP TIME (t
s
) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to
the PL transition from LOW-to-HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (t
h
) is defined as the minimum time following the
PL transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the
correct logic level may be released prior to the PL transition
from LOW-to-HIGH and still be recognized.
RECOVERY TIME (t
rec
) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
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