HI-6138 datasheet, PDF - EEWORLD Datasheet

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HI-6138: Description40 MHz SPI Host Interface; File Size4MB，254 Pages; ManufacturerHolt Integrated Circuits; Websitehttp://www.holtic.com/

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HI-6138 Overview

40 MHz SPI Host Interface

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MAMBA

: HI-6138

3.3V BC / MT / RT MIL-STD-1553 / MIL-STD-1760

September, 2015

Compact Multi-Terminal Device with SPI Host Interface

•

64-Word Interrupt Log Buffer queues the most

recent 32 interrupts. Hardware-assisted interrupt

decoding quickly identifies interrupt sources.

Built-in self-test for protocol logic, digital signal

paths and internal RAM.

Optional self-initialization at reset uses external

serial EEPROM.

±8kV ESD Protection (HBM, all pins).

GENERAL DESCPIPTION

The 3.3V CMOS HI-6138 device is a member of Holt’s

MIL-STD-1553 MAMBA

family and provides a complete

single- or multi-function interface between a host

processor and MIL-STD-1553B bus. Each IC contains

a Bus Controller (BC), a Bus Monitor Terminal (MT)

and a Remote Terminals (RT). Any combination of the

contained 1553 functions can be enabled for concurrent

operation. The enabled terminals communicate with the

MIL-STD-1553 buses through a shared on-chip dual

bus transceiver and external transformers. The user

allocates 16K bytes of on-chip static RAM between

devices to suit application requirements.

The HI-6138 communicates with the host via a 40 MHz

4-wire serial peripheral interface (SPI). Programmable

interrupts provide terminal status to the host processor.

Circular data buffers in RAM have interrupts for rollover

and programmable “level attained”.

The HI-6138 can be configured for automatic self-

initialization after reset. A dedicated SPI port reads

data from an external serial EEPROM to fully configure

registers and RAM and optionally start execution for any

subset of one to three terminal devices.

•

Two temperature ranges: -40 C to +85 C, or

-55 C to +125 C with optional burn-in.

RoHS compliant and Tin / Lead options available.

PIN CONFIGURATION (TOP)

48 - BCTRIG

47 - BENDI

46 - TEST

45 - BUSA

44 - VCCP

43 - BUSA

42 - BUSB

41 - VCCP

40 - BUSB

39 - MTSTOFF

38 - EE2K

37 - RTMC8

FEATURES

•

Concurrent multi-terminal operation for one to

three MIL-STD-1553B functions: BC, MT and/or

RT.

8K x 17-bit words internal static RAM with parity

Autonomous terminal operation requires minimal

host intervention.

40 MHz SPI Host Interface.

MIL-STD-1760 option sets Busy bit in Status

Word response during initialization.

World’s smallest MIL-STD-1553 terminal, QFN

package measures just 6mm x 6mm.

Fully programmable Bus Controller with 28 op

code instruction set.

Simple Monitor Terminal (SMT) Mode records

commands and data separately, with 16-bit or 48-

bit time tagging.

Independent 16-bit time tag counters and clock

sources for all modes. The Bus Controller and

Monitor also have 32- and 48-bit time count

options, respectively.

MODE - 1

IRQ - 2

ACKIRQ - 3

MODE1760 - 4

READY - 5

VCC - 6

GND - 7

ACTIVE - 8

RTSSF - 9

AUTOEN - 10

TXINHA - 11

TXINHB - 12

HI-6138PCIF

HI-6138PCTF

HI-6138PCMF

36 - TTCLK

35 - ESCLK

34 - EECOPY

33 - ECS

32 - MOSI

31 - VCC

30 - GND

29 - MISO

28 - MTTCLK

27 - LOCK

26 - RTA4

25 - RTA3

•

48 - Pin Plastic 6mm x 6mm

Chip-Scale Package (QFN)

See Section 26.1 on page 250 for 48-Pin PQFP Configuration

•

DS6138 Rev. A

HOLT INTEGRATED CIRCUITS

www.holtic.com

RTAP - 13

RTA0 - 14

CE - 15

VCC - 16

SCK - 17

SO - 18

SI - 19

GND - 20

MCLK - 21

RTA1 - 22

MR - 23

RTA2 - 24

09/15

HI-6138

Table of Contents

1. BLOCK DIAGRAM ........................................................................................... 14

2. FEATURE OVERVIEW ................................................................................... 15

2.1.

2.2.

2.3.

2.4.

2.5.

Bus Controller Operation .......................................................................................... 15

Remote Terminal Operation ...................................................................................... 15

Monitor Terminal Operation ....................................................................................... 15

Interrupts ................................................................................................................... 15

Reset and Initialization .............................................................................................. 15

3. PIN DESCRIPTIONS ....................................................................................... 16

4. MEMORY MAP................................................................................................. 19

5. RAM STRUCTURES ....................................................................................... 20

5.1.

5.2.

5.3.

5.4.

5.5.

5.6.

5.7.

5.8.

5.9.

5.10.

5.11.

5.12.

5.13.

5.14.

Interrupt Log Data Buffer .......................................................................................... 20

Bus Controller (BC) Instruction List........................................................................... 20

Bus Controller (BC) Msg Control / Status Stack ....................................................... 20

Bus Controller (BC) Call Stack.................................................................................. 20

Bus Controller (BC) General Purpose Queue ........................................................... 20

Monitor Terminal Temporary Buffers A & B ............................................................... 20

Monitor Terminal (MT) Address List .......................................................................... 20

Monitor Terminal (MT) Message Filter Table ............................................................. 21

Monitor Terminal (MT) Data Buffers .......................................................................... 21

RT Command Illegalization Table ............................................................................. 21

RT Descriptor Table .................................................................................................. 21

RT Temporary Receive Buffer ................................................................................... 21

RT Message Data Buffers ......................................................................................... 21

RT Storage for Mode Code Commands.................................................................... 21

6. HARDWARE FEATURES ................................................................................ 22

6.1.

6.2.

6.3.

6.4.

6.5.

Remote Terminal Address Inputs .............................................................................. 22

Dual Transceivers for MIL-STD-1553 Bus ................................................................ 22

Encoder and Decoders ............................................................................................. 22

Auto-Initialization Serial EEPROM Interface ............................................................. 22

Transmit Time-out Fail-Safe Counter ........................................................................ 22

HOLT INTEGRATED CIRCUITS

HI-6138

6.6.

MIL-STD-1760 Mode ................................................................................................ 22

7. REGISTER & MEMORY ADDRESSING .......................................................... 23

8. REGISTER DEFINITIONS ............................................................................... 23

9. REGISTERS USED BY ALL DEVICE FUNCTIONS ........................................ 28

9.1.

9.2.

9.3.

9.4.

9.5.

9.6.

9.7.

9.8.

Master Configuration Register 1 (0x0000) ................................................................ 28

Master Configuration Register 2 (0x004E) ............................................................... 31

Master Status and Reset Register (0x0001) ............................................................ 33

Overview of Interrupts ............................................................................................... 35

Hardware Interrupt Behavior ..................................................................................... 36

Interrupt Count & Log Address Register (0x000A) ................................................... 37

Interrupt Log Buffer ................................................................................................... 37

Hardware Interrupt Registers .................................................................................... 40

9.8.1.

9.8.2.

9.8.3.

Hardware Interrupt Enable Register (0x000F) ...................................................... 40

Hardware Pending Interrupt Register (0x0006) .................................................... 40

Hardware Interrupt Output Enable Register (0x0013) .......................................... 40

9.9.

9.10.

9.11.

9.12.

Extended Configuration Register (0x004D) .............................................................. 43

Time Tag Counter Configuration ............................................................................... 46

Time Tag Counter Configuration Register (0x0039).................................................. 47

Memory Address Pointer Registers .......................................................................... 51

10.

BUS CONTROLLER − CONFIGURATION AND OPERATION

........................ 53

10.1.

10.2.

10.3.

10.4.

Bus Controller Condition Codes................................................................................ 54

Bus Controller Instruction Op Codes ........................................................................ 57

Bus Controller General Purpose Queue ................................................................... 66

Bus Controller Message Control / Status Blocks ...................................................... 66

10.4.1.

10.4.2.

10.4.3.

10.4.4.

BC Control Word ................................................................................................... 67

Time to Next Message Word ................................................................................. 72

Data Block Pointer ................................................................................................. 72

BC Block Status Word ........................................................................................... 73

11. BUS CONTROLLER REGISTER DESCRIPTION .......................................... 77

11.1.

11.2.

11.3.

11.4.

BC (Bus Controller) Configuration Register (0x0032) ............................................... 77

Start Address Register for Bus Controller (BC) Instruction List (0x0033) ................. 86

Bus Controller (BC) Instruction List Pointer (0x0034) ............................................... 86

Bus Controller (BC) Frame Time Remaining Register (0x0035) ............................... 87

HOLT INTEGRATED CIRCUITS

HI-6138

11.5.

11.6.

11.7.

11.8.

11.9.

Bus Controller (BC) Time To Next Message Register (0x0036) ................................ 87

Bus Controller (BC) Condition Code Register (Read 0x0037) .................................. 87

Bus Controller (BC) General Purpose Flag Register (Write 0x0037) ........................ 90

Bus Controller (BC) General Purpose Queue Pointer Register (0x0038) ................. 90

Bus Controller (BC) Time Tag Counter (0x0043) ...................................................... 91

11.10. Bus Controller (BC) Time Tag Counter High (0x0044) .............................................. 91

11.11. Bus Controller (BC) Time Tag Utility Register (0x0045) ........................................... 92

11.12. Bus Controller (BC) Time Tag Utility High Register (0x0046) .................................. 92

11.13. Bus Controller (BC) Time Tag Match Register (0x0047) .......................................... 92

11.14. Bus Controller (BC) Time Tag Match High Register (0x0048) ................................. 92

11.15. Bus Controller Interrupt Registers and Their Use ..................................................... 92

11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010) ...................................... 94

11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007) .................................... 94

11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014) .......................... 94

12. SIMPLE MONITOR TERMINAL (SMT) ............................................................ 97

12.1.

12.2.

12.3.

Overview ................................................................................................................... 97

SMT Block Status Word (BSW) Description ........................................................... 102

SMT Message Filter Table ...................................................................................... 105

13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION ............. 107

13.1.

13.2.

13.3.

13.4.

13.5.

13.6.

13.7.

13.8.

13.9.

SMT Configuration Register (0x0029) .................................................................... 107

SMT Bus Monitor Address List Start Address Register (0x002F) ........................... 110

SMT Next Message Command Buffer Address (0x0030) ....................................... 110

SMT Last Message Command Buffer Address (0x0031) .........................................111

SMT Bus Monitor Time Tag Count Register (0x003A) .............................................111

SMT Bus Monitor Time Tag Count Mid Register (0x003B) ......................................111

SMT Bus Monitor Time Tag Count High Register (0x003C).....................................111

SMT Bus Monitor Time Tag Utility Register (0x003D) ............................................. 112

SMT Bus Monitor Time Tag Utility Mid Register (0x003E) ...................................... 112

13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F) ..................................... 112

13.11. SMT Bus Monitor Time Tag Match Register (0x0040) ............................................ 113

13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041) ..................................... 113

13.13. SMT Bus Monitor Time Tag Match High Register (0x0042) ................................... 113

13.14. SMT Bus Monitor Interrupt Registers and Their Use .............................................. 114

13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011) ......................................... 115

HOLT INTEGRATED CIRCUITS

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