R1QAA4418RBG datasheet, PDF - EEWORLD Datasheet

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R1QAA4418RBG: Description144-Mbit DDRII SRAM 2-word Burst; File Size494KB，37 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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R1QAA4418RBG Overview

144-Mbit DDRII SRAM 2-word Burst

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R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)

R1QBA4436RBG / R1QBA4418RBG

/ R1QBA4409RBG

R1QEA4436RBG / R1QEA4418RBG

/ R1QEA4409RBG

R1QHA4436RBG / R1QHA4418RBG / R1QHA4409RBG

R1QLA4436RBG / R1QLA4418RBG / R1QLA4409RBG

R10DS0189EJ0011

144-Mbit DDRII+ SRAM

2-word Burst

Description

The R1Q#A4436 is a 4,194,304-word by 36-bit and the R1Q#A4418 is a 8,388,608-word by 18-bit synchronous

double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are

controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products

are suitable for applications which require synchronous operation, high speed, low voltage, high density and

wide bit configuration. These products are packaged in 165-pin plastic FBGA package.

= B: Latency =2.5, w/o ODT

= E: Latency =2.5, w/ ODT

# = H: Latency =2.0, w/o ODT

# = L: Latency =2.0, w/ ODT

Preliminary

Rev. 0.11b

2012.06.05

Features

Power Supply

• 1.8 V for core (V

), 1.4 V to V

for I/O (V

DDQ

)

Clock

• Fast clock cycle time for high bandwidth

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems

• Clock-stop capability with s restart

I/O

• Common data input/output bus

• Pipelined double data rate operation

• HSTL I/O

• User programmable output impedance

• DLL/PLL circuitry for wide output data valid window and future frequency scaling

• Data valid pin (QVLD) to indicate valid data on the output

Function

• Two-tick burst for low DDR transaction size

• Internally self-timed write control

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

Package

• 165 FBGA package (15 x 17 x 1.4 mm)

Notes:

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress

Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)

2. The specifications of this device are subject to change without notice. Please contact your nearest

Renesas Electronics Sales Office regarding specifications.

3. Refer to

"http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp"

for the latest and detailed information.

4. Descriptions about x9 parts in this datasheet are just for reference.

Rev. 0.11b : 2012.06.05

R10DS0189EJ0011

PAGE : ‹#›

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Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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