NCV7519, NCV7519A
FLEXMOS] Hex Low-side
MOSFET Pre-driver
The NCV7519/A programmable six channel low−side MOSFET
pre−driver is one of a family of FLEXMOS automotive grade products
for driving logic−level MOSFETs. The product is controllable by a
combination of serial SPI and parallel inputs. The device offers 3.3 V/
5 V compatible inputs and the serial output driver can be powered
from either 3.3 V or 5 V. An internal power−on reset provides
controlled power up. A reset input allows external re−initialization and
an enable input allows all outputs and diagnostics to be simultaneously
disabled.
Each channel independently monitors its external MOSFET’s drain
voltage for fault conditions. Shorted load fault detection thresholds are
fully programmable using an externally programmed reference
voltage and a combination of discrete internal ratio values. The ratio
values are SPI selectable and allow different detection thresholds for
each channel.
Fault recovery operation for each channel is programmable and may
be selected for latch−off or automatic retry. Status information for
each channel is 3−bit encoded by fault type and is available through
SPI communication.
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
Features
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QFN32
MW SUFFIX
CASE 488AM
QFN32
MW SUFFIX
CASE 485CZ
MARKING DIAGRAM
1
NCV7519x
AWLYYWWG
G
•
•
•
•
•
•
•
•
•
•
•
•
16−bit SPI with Parity and Frame Error Detection
3.3 V/5 V Compatible Parallel and Serial Control Inputs
3.3 V/5 V Compatible Serial Output Driver
Reset and Enable Inputs
Open−drain Fault Flag
Priority Encoded Diagnostics with Latched Unique Fault Type Data
♦
Shorted Load, Short to GND
♦
Open Load
♦
On and Off State Pulsed Mode Diagnostics
Ratiometric Diagnostic References and Currents
Programmable
♦
Shorted Load Fault Detection Thresholds
♦
Fault Recovery Mode
♦
Blanking Timers
Wettable Flanks Pb−Free Packaging
Commercial Vehicle Capable
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This is a Pb−Free Device
x
A
WL
YY
WW
G
= blank or A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 36 of this data sheet.
Benefits
•
Scalable to Load by Choice of External MOSFET
©
Semiconductor Components Industries, LLC, 2015
1
August, 2015 − Rev. 2
Publication Order Number:
NCV7519/D
NCV7519, NCV7519A
IN5 IN4 IN3 IN2 IN1 IN0
ENB
VCC2
NCV7519
Hex MOSFET Pre-Driver
VREG
3V
INTERNAL
RAIL
RAIL
CHANNEL0
DRN0
VCC1
POWER ON RESET
&
POR
BIAS
DRN
FAULT
DETECT
VSS
REF
DISABLE
DRIVER
VCC2
GAT0
RSTB
RST
ENB
VSS
RAIL
CONTROL
REGISTERS
DRN
REF
DISABLE
PARALLEL
SERIAL
RST ENB VCC2
CHANNEL1
DRN1
CSB
DRN
RST ENB VCC2
REF
RST
CSB
SCLK
DISABLE
PARALLEL
SERIAL
IREF
VSS
GAT1
DRN2
CHANNEL2
SCLK
SI
SI
GAT2
RST ENB VCC2
SPI
16 BIT
DRN
REF
DISABLE
PARALLEL
SERIAL
CHANNEL3
VDD
DRN3
SO
DRIVER
SO
DRN
RST ENB VCC2
GAT3
CHANNEL4
VSS
REF
DISABLE
RST
PARALLEL
SERIAL
DRN4
FAULT DATA
FLTB
CSB
RST
DRN
DISABLE
DRN
REF
DISABLE
PARALLEL
SERIAL
RST ENB VCC2
IREF
VSS
GAT4
DRN5
FAULT LOGIC
&
REFRESH TIMER
CLOCK
CHANNEL5
GAT5
GND
RST
RST ENB
RST
VCC1
FLTREF
+
FAULT REFERENCE
GENERATOR
REF
REF
OFF−
STATE
DIAGNOSTICS
GENERATOR
VSS
−
OA
VLOAD
Figure 1. Block Diagram
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2
NCV7519, NCV7519A
REVERSE
BATTERY
&
TRANSIENT
PROTECTION
VBAT
V
LOAD
UNCLAMPED LOAD
CB2
CB3
+5V
R
FILT
CB1
M
POWER-ON
RESET
+5V OR
+3.3V
VLOAD
VCC1
RSTB
VCC2
DRN0
GAT0
DRN1
GAT1
DRN2
R
D2
*
R
D1
*
R
D0
*
RST
ENB
IN0
HOST CONTROLLER
PARALLEL
IN1
NCV7519
IN2
IN3
GAT2
DRN3
GAT3
DRN4
GAT4
DRN5
GAT5
VDD
SO
VSS
R
D5
*
R
D4
*
R
D3
*
SPI
IN4
IN5
FLTB
CSB
RX1
SCLK
SI
FLTREF
RX2
GND
IRQ
R
FPU
* Optional R
DX
- See Application Guidelines
Figure 2. Application Diagram
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3
NCV7519, NCV7519A
PACKAGE
PIN DESCRIPTION 32 PIN QFN EXPOSED PAD PACKAGE
Label
FLTREF
DRN0 − DRN5
GAT0 − GAT5
RSTB
ENB
IN0 − IN5
CSB
SCLK
SI
SO
FLTB
VLOAD
VCC1
GND
VCC2
VDD
VSS
EP
Analog Fault Detect Threshold: 5 V Compliant
Analog Drain Feedback
Analog Gate Drive: 5 V Compliant
Digital Master Reset Input: 3.3 V/5 V (TTL) Compatible
Digital Master Enable Input: 3.3 V/5 V (TTL) Compatible
Digital Parallel Input: 3.3 V/5 V (TTL) Compatible
Digital Chip Select Input: 3.3 V/5 V (TTL) Compatible
Digital Shift Clock Input: 3.3 V/5 V (TTL) Compatible
Digital Serial Data Input: 3.3 V/5 V (TTL) Compatible
Digital Serial Data Output: 3.3 V/5 V Compliant
Digital Open−Drain Output: 3.3 V/5 V Compliant
Power Supply − Diagnostic References and Currents
Power Supply − Low Power Path
Power Return − Low Power Path − Device Substrate
Power Supply − Gate Drivers
Power Supply − Serial Output Driver
Power Return − VLOAD, VCC2, VDD
Exposed Pad − Connected to GND − Device Substrate
FLTREF
Description
DRN0
DRN1
VCC1
VCC2
GAT0
GAT1
GND
32
IN0
IN1
IN2
IN3
IN4
IN5
ENB
RSTB
1
2
3
4
31
30
29
28
27
26
25
Exposed Pad
(EP)
24 GAT2
23 DRN2
22 GAT3
21 DRN3
NCV7519
20 GAT4
19 DRN4
18 GAT5
17 DRN5
9
FLTB
10
CSB
11
SCLK
12
SI
13
SO
14
VDD
15
VSS
16
VLOAD
5
6
7
8
Figure 3. 32 Pin QFN Exposed Pad Pinout (Top View)
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4
NCV7519, NCV7519A
MAXIMUM RATINGS
(Voltages are with respect to device substrate.)
Rating
DC Supply − V
LOAD
DC Supply − V
CC1
, V
CC2
, V
DD
Difference Between V
CC1
and V
CC2
Difference Between GND (Substrate) and V
SS
Drain Input Clamp Forward Voltage Transient (≤2 ms,
≤1%
duty)
Drain Input Clamp Forward Current Transient (≤2 ms,
≤1%
duty)
Drain Input Clamp Energy Repetitive (≤2 ms,
≤1%
duty)
Drain Input Clamp Reverse Current V
DRNX
≥
−1.0 V
Input Voltage (Any Input Other Than Drain)
Output Voltage (Any Output)
Junction Temperature, T
J
Storage Temperature, T
STG
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C (Note 1)
Value
−0.3 to 45
−0.3 to 5.8
±0.3
±0.3
78
10
1.56
−50
−0.3 to 5.8
−0.3 to 5.8
−40 to 150
−65 to 150
260 peak
Unit
V
V
V
V
V
mA
mJ
mA
V
V
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ATTRIBUTES
Characteristic
ESD Capability
Human Body Model per AEC−Q100−002
Machine Model per AEC−Q100−003
Moisture Sensitivity
Package Thermal Resistance − Still−air
Junction−to−Ambient, Rq
JA
Junction−to−Exposed Pad, RY
JPAD
2.
3.
4.
5.
(Note 2)
(Note 4)
(Note 5)
Drain Feedback Pins (Note 3)
All Other Pins
Value
≥ ±4.0
kV
≥ ±2.0
kV
≥ ±200
V
MSL3
95°C/W
46°C/W
3.2°C/W
See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
With GND & V
SS
pins tied together − path between drain feedback pins and GND, or between drain feedback pins.
Based on JESD51−3, 1.2 mm thick FR4, 2S0P PCB, 2 oz. signal, 20 thermal vias to 400 mm
2
spreader on bottom layer.
Based on JESD51−7, 1.2 mm thick FR4, 1S2P PCB, 2 oz. signal, 20 thermal vias to 80 x 80 mm 1 oz. internal spreader planes.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
LOAD
V
DRNX
V
CC1
V
CC2
V
DD
V
FLTREF
V
IN
High
V
IN
Low
T
A
t
RESET
Parameter
Diagnostic References and Currents Power Supply Voltage
Drain Input Feedback Voltage
Main Power Supply Voltage
Gate Drivers Power Supply Voltage
Serial Output Driver Power Supply Voltage
Fault Detect Threshold Reference Voltage
Logic High Input Voltage
Logic Low Input Voltage
Ambient Still−air Operating Temperature
Startup Delay at Power−on Reset (POR) (Note 6)
MIN
7.5
−0.3
4.75
V
CC1
− 0.3
3.0
0.35
2.0
0
−40
500
MAX
36.0
60
5.25
V
CC1
+ 0.3
V
CC1
2.75
V
CC1
0.8
125
−
Unit
V
V
V
V
V
V
V
V
°C
ms
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Minimum wait time until device is ready to accept serial input data.
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