BelaSigna 300
Audio Processor for Portable
Communication Devices
Introduction
BelaSigna
®
300 is a DSP−based mixed−signal audio processing
system that delivers superior audio clarity without compromising size
or battery life. The processor is specifically designed for monaural
portable communication devices requiring high performance audio
processing capabilities and programming flexibility when form−factor
and power consumption are key design constraints.
The efficient dual−MAC 24−bit CFX DSP core, together with the
HEAR configurable accelerator signal processing engine, high speed
debugging interface, advanced algorithm security system, state−of−
the−art analog front end, Class D output stage and much more,
constitute an entire system on a single chip, which enables
manufacturers to create a range of advanced and unique products. The
system features a high level of instructional parallelism, providing
highly efficient computing capability. It can simultaneously execute
multiple advanced adaptive noise reduction and echo cancellation
algorithms, and uses an asymmetric dual−core patented architecture to
allow for more processing in fewer clock cycles, resulting in reduced
power consumption.
BelaSigna 300 is supported by a comprehensive suite of
development tools, hands−on training, full technical support and a
network of solution partners offering software and engineering
services to help speed product design and shorten time to market.
www.onsemi.com
DFN−44
D SUFFIX
CASE 506BU
WLCSP−35
W SUFFIX
CASE 567AG
MARKING DIAGRAM
BELASIGNA300
35−02−G
XXXXYZZ
BELASIGNA300 = Device Code
35
= Number of Balls
02
= Revision of Die
G
= Pb−Free
XXXX
= Date Code
Y
= Assembly Plant Identifier
=
(May be Two Characters)
ZZ
= Traceability Code
Key Features
•
Flexible DSP−based System:
a complete DSP−based, mixed−signal
audio system consisting of the CFX core, a fully programmable,
highly cycle−efficient, dual−Harvard architecture 24−bit DSP
utilizing explicit parallelism; the HEAR configurable accelerator for
optimized signal processing; and an efficient input/output controller
(IOC) along with a full complement of peripherals and interfaces,
which optimize the architecture for audio processing at extremely
low power consumption
Ultra−low−power:
typically 1−5 mA
Excellent Audio Fidelity:
up to 110 dB input dynamic range,
exceptionally low system noise and low group delay
Miniature Form Factor:
available in a miniature 3.63 mm x
2.68 mm x 0.92 mm (including solder balls) WLCSP package. In
addition, BelaSigna 300 is also available in a bigger DFN package
allowing easier assembly and PCB routing
Multiple Audio Input Sources:
four input channels from five input
sources (depends on package selection) can be used simultaneously
for multiple microphones or direct analog audio inputs
Full Range of Configurable Interfaces:
including a fast I
2
C−based
interface for download, debug and general communication, a highly
configurable PCM interface to stream data into and out of the device,
a high−speed UART, an SPI port and 5 GPIOs
ORDERING INFORMATION
Device
B300W35A109XXG
B300D44A103XXG
Package
WLCSP
(Pb−Free)
DFN
(Pb−Free)
Shipping
†
2500 / Tape &
Reel
2500 / Tape &
Reel
•
•
•
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
•
•
©
Semiconductor Components Industries, LLC, 2015
1
February, 2015 − Rev. 8
Publication Order Number:
B300/D
BelaSigna 300
•
Integrated A/D Converters and Powered Output:
minimize need for external components
•
Flexible Clocking Architecture:
supports speeds up to
40 MHz
•
“Smart” Power Management:
including low current
standby mode requiring only 0.06 mA
•
Diverse Memory Architecture:
4864x48−bit words of
shared memory between the CFX core and the HEAR
accelerator plus 8−Kword DSP core data memory,
12−Kwords of 32−bit DSP core program memory as
well as other memory banks
Contents
•
Data Security:
sensitive program data can be
encrypted for storage in external NVRAM to prevent
unauthorized parties from gaining access to proprietary
software intellectual property, 128−bit AES encryption
•
Development Tools:
interface hardware with USB
support as well as a full IDE that can be used for every
step of program development including testing and
debugging
•
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figures and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Mechanical Information and Circuit Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Assembly Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
www.onsemi.com
2
BelaSigna 300
Figures and Data
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage at any input pin
Operating supply voltage (Note 1)
Operating temperature range (Note 2)
Storage temperature range (Note 3)
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Functional operation only guaranteed below 0°C for digital core (VDDC) and system voltages above 1.0 V.
2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50°C.
3. Extended range −55 to 125°C for storage temperature is under qualification.
Min
−0.3
0.9
−40
−55
Max
2.0
2.0
85
85
Unit
V
V
°C
°C
Electrical Performance Specifications
The tests were performed at 20°C with a clean 1.8 V supply voltage. BelaSigna 300 was running in low voltage mode (VDDC = 1.2 V).
The system clock (SYS_CLK) was set to 5.12 MHz and the sampling frequency is 16 kHz unless otherwise noted.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 2. ELECTRICAL SPECIFICATIONS
Description
OVERALL
Supply voltage
V
BAT
The WLCSP package option
will not operate properly below
1.8 V if it relies on an external
EEPROM powered by VBAT.
Filterbank, 100% CFX usage,
5.12 MHz, 16 kHz
Ambient room temperature
WDRC, VBAT = 1.8 V
Excludes output drive current
Ambient room temperature
AEC, VBAT = 1.8 V
Excludes output drive current
Ambient room temperature
Theoretical maximum
Excludes output drive current
Ambient room temperature
Deep Sleep current
Ambient room temperature,
VBAT = 1.25 V
Deep Sleep current
Ambient room temperature,
VBAT = 1.8 V
VREG (1
mF
External Capacitor)
Regulated voltage output
Regulator PSRR
Load current
Load regulation
Line regulation
VDBL (1
mF
External Capacitor)
Regulated doubled voltage
output
VDBL
1.9
2.0
2.1
V
√
V
REG
V
REG_PSRR
I
LOAD
LOAD
REG
LINE
REG
1 kHz
0.95
50
−
−
−
1.00
55
−
6.1
2
1.05
−
2
6.5
5
V
dB
mA
mV/mA
mV/V
√
√
0.9
1.8
2.0
V
√
Symbol
Conditions
Min
Typ
Max
Units
Screened
Current consumption
I
BAT
−
750
−
mA
√
−
600
−
mA
√
−
2.1
−
mA
√
−
10
−
mA
−
26
40
mA
−
62
160
mA
√
4. DFN Package option can have higher input−referred noise up to 2
mV
worse than the WLCSP. WLCSP specifications listed.
5. CDM only applies to the DFN package.
www.onsemi.com
3
BelaSigna 300
Table 2. ELECTRICAL SPECIFICATIONS
(continued)
Description
VDBL (1
mF
External Capacitor)
Regulator PSRR
Load current
Load regulation
Line regulation
VDDC (1
mF
External Capacitor)
Digital supply voltage output
VDDC output level adjustment
Regulator PSRR
Load current
Load regulation
Line regulation
POWER−ON−RESET (POR)
POR startup voltage
POR shutdown voltage
POR hysteresis
POR duration
INPUT STAGE
Analog input voltage
Preamplifier gain tolerance
Input impedance
V
IN
PAG
R
IN
1 kHz
0 dB preamplifer gain
Non−zero preamplifier gains
Input referred noise
IN
IRN
Unweighted,
100 Hz to 10 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB (Note 4)
1 kHz, 20 Hz to 8 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
Any valid preamplifier gain, 1 kHz
0
−1
−
550
−
0
239
578
2
1
−
615
V
dB
kW
kW
mVrms
√
√
√
VDDC
STARTUP
VDDC
SHUTDOWN
POR
HYSTERESIS
T
POR
0.775
0.755
13.8
11.0
0.803
0.784
19.1
11.6
0.837
0.821
22.0
12.3
V
V
mV
ms
VDDC
VDDC
STEP
VDDC
PSRR
I
LOAD
LOAD
REG
LINE
REG
1 kHz
Configured by a control register
0.79
27
25
−
−
−
0.95
29
25.5
−
3
3
1.25
31
26
3.5
12
8
V
mV
dB
mA
mV/mA
mV/V
√
√
VDBL
PSRR
I
LOAD
LOAD
REG
LINE
REG
1 kHz
35
−
−
−
41
−
7
10
−
2.5
10
20
dB
mA
mV/mA
mV/V
√
Symbol
Conditions
Min
Typ
Max
Units
Screened
−
−
−
−
−
−
−
−
39
10
7
6
4.5
4
3.5
3
50
12
9
8
5.5
5
4.5
4
dB
Input dynamic range
IN
DR
85
84
84
83
82
81
80
78
−
89
88
88
87
86
85
83
81
−70
−
−
−
−
−
−
−
−
−63
dB
√
Input peak THD+N
IN
THDN
4. DFN Package option can have higher input−referred noise up to 2
mV
worse than the WLCSP. WLCSP specifications listed.
5. CDM only applies to the DFN package.
www.onsemi.com
4
BelaSigna 300
Table 2. ELECTRICAL SPECIFICATIONS
(continued)
Description
DIRECT DIGITAL OUTPUT
Maximum load current
Output impedance
Output dynamic range
Output THD+N
Output voltage
I
DO
R
DO
DO
DR
DO
THDN
DO
VOUT
Normal mode
Normal mode
Unweighted, 100 Hz to 8 kHz
BW, mono
Unweighted, 100 Hz to 22 kHz
BW, mono
−
−
92
−
−V
BATRCVR
−
−
95
−79
50
5.5
−
−76
V
BATRCVR
mA
W
dB
dB
V
√
Symbol
Conditions
Min
Typ
Max
Units
Screened
ANTI−ALIASING FILTERS (Input and Output)
Preamplifier filter cut−off
frequency
Digital anti−aliasing filter
cut−off frequency
Passband flatness
Input stopband attenuation
LOW−SPEED A/D
Input voltage
INL
DNL
Maximum variation over tem-
perature (0°C to 50°C)
Sampling frequency
Channel sampling frequency
DIGITAL PADS
Voltage level for high input
Voltage level for low input
Voltage level for high output
Voltage level for low output
Input capacitance for digital
pads
Pull−up resistance for digital
input pads
Pull−down resistance for
digital input pads
Sample rate tolerance
Rise and fall time
ESD
V
IH
V
IL
V
OH
V
OL
C
IN
R
UP_IN
R
DOWN_IN
FS
Tr, Tf
Sample rate of 16 kHz or 32 kHz
Digital output pad
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
(Note 5)
Latch−up
V < GNDC, V > VBAT
2
200
500
200
kV
V
V
mA
2 mA source current
2 mA sink current
VBAT
* 0.8
−
VDDO
* 0.8
−
−
220
220
−1
−
−
−
−
4
270
270
±0
−
VBAT
* 0.2
−
VDDO
* 0.2
−
320
320
+1
V
V
V
V
pF
kW
kW
%
√
√
√
√
√
√
All channels sequentially
8 channels
Peak input voltage
From GND to 2*VREG
From GND to 2*VREG
0
−
−
−
−
−
−
4
−
−
12.8
1.6
2.0
10
2
5
−
−
V
LSB
LSB
LSB
kHz
kHz
√
60 kHz (12 kHz cut−off)
Preamp not bypassed
−
−
−1
−
20
f
s
/2
−
60
−
−
1
−
dB
dB
√
kHz
√
√
4. DFN Package option can have higher input−referred noise up to 2
mV
worse than the WLCSP. WLCSP specifications listed.
5. CDM only applies to the DFN package.
www.onsemi.com
5
京公网安备 11010802033920号
EEWORLD
