NB3U1548C
3.3V/2.5V/1.8V/1.5V 160 MHz
1:4 LVCMOS/LVTTL Low
Skew Over Voltage Tolerant
Fanout Buffer
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Description
The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout
buffer targeted for clock generation in high performance
telecommunication, networking and computing applications. The
device is optimized for low skew clock distribution in low voltage
applications. The input overvoltage tolerance enables using this
device in mixed mode voltage applications. An output enable pin
controls whether the outputs are in the active or high impedance state.
Guaranteed output skew characteristics make the NB3U1548C ideal
for those applications demanding well defined performance and
repeatability. The NB3U1548C is packaged in a small SOIC−8 and in
an TSSOP−8 package.
Features
MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
8
1548C
ALYWG
G
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948S
154
YWW
AG
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
•
Low skew 1:4 Fanout Buffer
Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies
LVCMOS Input and Output Levels
3.6 V Overvoltage Tolerance at the Clock and Control Inputs
Supports Clock Frequencies up to 160 MHz
LVCMOS Compatible Control Input for Output Disable
Output Disabled to a High Impedance State
−40°C to 85°C Ambient Operating Temperature
Available in Pb−Free RoHS Compliant Packages (SOIC−8,
TSSOP−8)
•
These Devices are Pb−Free and are RoHS Compliant
A
L
Y
W, WW
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2017
1
January, 2017 − Rev. 4
Publication Order Number:
NB3U1548C/D
NB3U1548C
CLK_IN
Q1
Q2
Q3
1
2
3
4
8
7
6
5
OE
V
DD
GND
Q4
Figure 2. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTIONS
Number
1
2
3
4
5
6
7
8
NOTE:
Name
CLK_IN
Q1
Q2
Q3
Q4
GND
V
DD
OE
Input
Output
Output
Output
Output
Power
Power
Input
Pullup
Type
Pulldown
Description
Single−ended clock input. LVCMOS interface levels.
Single−ended clock output. LVCMOS interface levels.
Single−ended clock output. LVCMOS interface levels.
Single−ended clock output. LVCMOS interface levels.
Single−ended clock output. LVCMOS interface levels.
Power supply ground.
Power supply pin.
Output enable pin. See Table 3. LVCMOS interface levels.
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. PIN CHARACTERISTICS
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
V
DD
= 3.465 V
V
DD
= 2.375 V
V
DD
= 1.95 V
V
DD
= 1.6 V
R
PULLUP
R
PULLDOWN
R
OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.3 V
±
5%
V
DD
= 2.5 V
±
5%
V
DD
= 1.8 V
±
0.15 V
V
DD
= 1.5
±
0.1 V
Test Conditions
Min
Typ
4
14
13
13
12
51
51
9
10
12
15
Max
Units
pF
pF
pF
pF
pF
kW
kW
W
W
W
W
Function Table
Table 3. OE CONFIGURATION TABLE
Input
OE
0
1 (default)
NOTE:
Operation
Q[4:1] disabled (high−impedance)
Q[4:1] enabled
OE is an asynchronous control.
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NB3U1548C
Table 4. ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
8 Lead SOIC
8 Lead TSSOP
Storage Temperature, T
STG
4.6 V
3.6 V
−0.5 V to V
DD
+ 0.5 V
102.5°C/W (0 mps)
151.2°C/W (0 mps)
−65°C to 150°C
Rating
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 6 cm
2
copper area.
2. For additional information, see Application Note AND8003/D.
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3 V
+
5%, T
A
= −405C to 855C
V
DD
I
DDQ
Power Supply Voltage
Quiescent Power Supply Current
Inputs Open, Outputs
Unloaded
3.135
3.3
3.465
1
V
mA
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 2.5 V
+
5%, T
A
= −405C to 855C
V
DD
I
DDQ
Power Supply Voltage
Quiescent Power Supply Current
Inputs Open, Outputs
Unloaded
2.375
2.5
2.625
1
V
mA
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 1.8 V
+
0.15 V, T
A
= −405C to 855C
V
DD
I
DDQ
Power Supply Voltage
Quiescent Power Supply Current
Inputs Open, Outputs
Unloaded
1.65
1.8
1.95
1
V
mA
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 1.5 V
+
0.1 V, T
A
= −405C to 855C
V
DD
I
DDQ
Power Supply Voltage
Quiescent Power Supply Current
Inputs Open, Outputs
Unloaded
1.4
1.5
1.6
1
V
mA
LVCMOS DC CHARACTERISTICS, V
DD
= 3.3 V
+
5%, T
A
= −405C to 855C
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
CLK_IN
OE
I
IL
Input Low Current
CLK_IN
OE
V
OH
V
OL
Output High Voltage
Output Low Voltage
Q[4:1]
Q[4:1]
V
DD
= V
IN
= 3.465 V
V
DD
= V
IN
= 3.465 V
V
DD
= 3.465 V, V
IN
= 0 V
V
DD
= 3.465 V, V
IN
= 0 V
I
OH
= −12 mA
I
OL
= 12 mA
−5
−150
2.6
0.5
0.65 * V
DD
−0.3
3.6
0.35 * V
DD
165
5
V
V
mA
mA
mA
mA
V
V
LVCMOS DC CHARACTERISTICS, V
DD
= 2.5 V
+
5%, T
A
= −405C to 855C
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
CLK_IN
OE
I
IL
Input Low Current
CLK_IN
OE
V
DD
= V
IN
= 2.625 V
V
DD
= V
IN
= 2.625 V
V
DD
= 2.625 V, V
IN
= 0 V
V
DD
= 2.625 V, V
IN
= 0 V
−5
−150
0.65 * V
DD
−0.3
3.6
0.35 * V
DD
165
5
V
V
mA
mA
mA
mA
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NB3U1548C
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
LVCMOS DC CHARACTERISTICS, V
DD
= 2.5 V
+
5%, T
A
= −405C to 855C
V
OH
V
OL
Output High Voltage
Output Low Voltage
Q[4:1]
Q[4:1]
I
OH
= −12 mA
I
OL
= 12 mA
1.8
0.5
V
V
LVCMOS DC CHARACTERISTICS, V
DD
= 1.8 V
+
0.15 V, T
A
= −405C to 855C
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
CLK_IN
OE
I
IL
Input Low Current
CLK_IN
OE
V
OH
V
OL
Output High Voltage
Output Low Voltage
Q[4:1]
Q[4:1]
V
DD
= 1.95 V, V
IN
= 0 V
V
DD
= 1.95 V, V
IN
= 0 V
I
OH
= −6 mA
I
OL
= 6 mA
−5
−150
V
DD
– 0.45
0.45
V
DD
= V
IN
= 1.95 V
0.65 * V
DD
−0.3
3.6
0.35 * V
DD
165
5
V
V
mA
mA
mA
mA
V
V
LVCMOS DC CHARACTERISTICS, V
DD
= 1.5 V
+
0.1 V, T
A
= −405C to 855C
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
CLK_IN
OE
I
IL
Input Low Current
CLK_IN
OE
V
OH
V
OL
Output High Voltage
Output Low Voltage
Q[4:1]
Q[4:1]
V
DD
= V
IN
= 1.6 V
V
DD
= V
IN
= 1.6 V
V
DD
= 1.6 V, V
IN
= 0 V
V
DD
= 1.6 V, V
IN
= 0 V
I
OH
= −4 mA
I
OL
= 4 mA
−5
−150
0.75 * V
DD
0.25 * V
DD
0.65 * V
DD
−0.3
3.6
0.35 * V
DD
165
5
V
V
mA
mA
mA
mA
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NB3U1548C
Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
AC CHARACTERISTICS, V
DD
= 3.3 V
+
5%, T
A
= −405C to 855C
f
OUT
tp
LH
tp
HL
t
PLZ
, t
PHZ
t
PZL
, t
PZH
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Output Frequency
Propagation Delay
(low to high transition); (Notes 4, 8)
Propagation Delay
(high to low transition); (Notes 4, 8)
Disable Time, (active to high−impedance)
Enable Time, (high−impedance to active)
Output Skew; (Notes 5, 6)
Part−to−Part Skew; (Notes 5, 7)
Buffer Additive Phase Jitter, RMS
Output Rise/Fall Time
Output Duty Cycle
25 MHz, Integration Range:
12 kHz − 5 MHz
10% to 90%
0.33
48
0.094
1.2
53
0.7
0.7
160
2.1
2.1
10
10
250
800
MHz
ns
ns
ns
ns
ps
ps
ps
ns
%
AC CHARACTERISTICS, V
DD
= 2.5 V
+
5%, T
A
= −405C to 855C
f
OUT
tp
LH
tp
HL
t
PLZ
, t
PHZ
t
PZL
, t
PZH
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Output Frequency
Propagation Delay
(low to high transition); (Notes 4, 8)
Propagation Delay
(high to low transition); (Notes 4, 8)
Disable Time (active to high−impedance)
Enable Time (high−impedance to active)
Output Skew; (Notes 5, 6)
Part−to−Part Skew; (Notes 5, 7)
Buffer Additive Phase Jitter, RMS
Output Rise/Fall Time
Output Duty Cycle
25 MHz, Integration Range:
12 kHz − 5 MHz
10% to 90%
0.33
45
0.076
1.2
53
0.8
0.8
160
2.0
2.0
10
10
250
800
MHz
ns
ns
ns
ns
ps
ps
ps
ns
%
AC CHARACTERISTICS, V
DD
= 1.8 V
+
0.15 V, T
A
= −405C to 855C
f
OUT
tp
LH
tp
HL
t
PLZ
, t
PHZ
t
PZL
, t
PZH
tsk(o)
tsk(pp)
tjit
Output Frequency
Propagation Delay
(low to high transition); (Notes 4, 8)
Propagation Delay
(high to low transition); (Notes 4, 8)
Disable Time (active to high−impedance)
Enable Time (high−impedance to active)
Output Skew; (Notes 5, 6)
Part−to−Part Skew; (Notes 5, 7)
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5MHz
0.193
1.1
1.1
160
2.8
2.8
10
10
250
800
MHz
ns
ns
ns
ns
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Characterized up to F
OUT
≤
150 MHz.
4. Measured from the V
DD
/2 of the input to V
DD
/2 of the output.
5. This parameter is defined in accordance with JEDEC Standard 65.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
8. With rail to rail input clock.
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