KAI-04070
2048 (H) x 2048 (V) Interline
CCD Image Sensor
Description
The KAI−04070 Image Sensor is a 4-megapixel CCD in a 4/3 inch
optical format. Based on the TRUESENSE 7.4 micron Interline
Transfer CCD Platform, the sensor provides very high smear rejection
and up to 82 dB linear dynamic range through the use of a unique
dual-gain amplifier. A flexible readout architecture enables use of 1, 2,
or 4 outputs for full resolution readout up to 28 frames per second,
while a vertical overflow drain structure suppresses image blooming
and enables electronic shuttering for precise exposure control.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Interline CCD, Progressive Scan
2128 (H)
×
2112 (V)
2080 (H)
×
2080 (V)
2048 (H)
×
2048 (V)
7.4
mm
(H)
×
7.4
mm
(V)
15.2 mm (H)
×
15.2 mm (V),
21.4 mm (Diagonal),
4/3″ Optical Format
1:1
1, 2, or 4
44,000 electrons
8.7
mV/e
−
(Low), 33
mV/e
−
(High)
52%
38%, 42%, 43%
37%, 42%, 41%
12 e
−
rms
3 e
−
/s
145 e
−
/s
7°C
9°C
70 dB
82 dB
0.999999
> 1000 X
−115 dB
< 10 electrons
40 MHz
28 fps
14 fps
8 fps
68 Pin PGA
AR Coated, 2 Sides
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Figure 1. KAI−04070 Interline CCD
Image Sensor
Features
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Pan (−ABA, −PBA, −QBA)
R, G, B (−CBA)
R, G, B (−FBA)
Read Noise (f = 40 MHz)
Dark Current
Photodiode
VCCD
Dark Current Doubling Temp.
Photodiode
VCCD
Dynamic Range
High Gain Amp (40 MHz)
Dual Amp, 2×2 Bin (40 MHz)
Charge Transfer Efficiency
Blooming Suppression
Smear
Image Lag
Maximum Pixel Clock Speed
Maximum Frame Rate
Quad Output
Dual Output
Single Output
Package
Cover Glass
•
Superior Smear Rejection
•
Up to 82 dB Linear Dynamic Range
•
Bayer Color Pattern, TRUESENSE Sparse
•
•
•
•
Color Filter Pattern, and Monochrome
Configurations
Progressive Scan & Flexible Readout
Architecture
High Frame Rate
High Sensitivity − Low Noise Architecture
Package Pin Reserved for Device
Identification
Application
•
Industrial Imaging and Inspection
•
Traffic
•
Surveillance
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
©
Semiconductor Components Industries, LLC, 2015
1
July, 2015 − Rev. 3
Publication Order Number:
KAI−04070/D
KAI−04070
The sensor is available with the TRUESENSE Sparse
Color Filter Pattern, a technology which provides a 2x
improvement in light sensitivity compared to a standard
color Bayer part.
The sensor shares common pin-out and electrical
configurations with a full family of Truesense Imaging
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−04070 IMAGE SENSOR
Part Number
KAI−04070−ABA−JD−BA
KAI−04070−ABA−JD−AE
KAI−04070−ABA−JR−BA
KAI−04070−ABA−JR−AE
11KAI−04070−FBA−JD−BA
11KAI−04070−FBA−JD−AE
11KAI−04070−QBA−JD−BA
11KAI−04070−QBA−JD−AE
11KAI−04070−CBA−JD−BA*
11KAI−04070−CBA−JD−AE*
11KAI−04070−PBA−JD−BA*
11KAI−04070−PBA−JD−AE*
Description
Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Gen2 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen2 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Gen1 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen1 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Marking Code
Interline Transfer CCD image sensors, allowing a single
camera design to be leveraged in support of multiple
devices.
KAI−04070−ABA
Serial Number
KAI−04070−FBA
Serial Number
KAI−04070−QBA
Serial Number
KAI−04070−CBA
Serial Number
KAI−04070−PBA
Serial Number
*Note recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
G2−FPGA−BD−14−40−A−GEVK
KAI−68PIN−HEAD−BD−A−GEVB
LENS−MOUNT−KIT−A−GEVK
KAI−68PIN−N−PROBE−CARD−A−GEVB
KAI−68PIN−W−PROBE−CARD−A−GEVB
Description
FPGA Board for IT−CCD Evaluation Hardware
68 Pin Imager Board for IT−CCD Evaluation Hardware
Lens Mount Kit for IT−CCD Evaluation Hardware
68 Pin Probe Card (Narrow Socket)
68 Pin Probe Card (Wide Socket)
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−04070
DEVICE DESCRIPTION
Architecture
SUB
RDcd
R2cd
R1c
VDDc
VOUTc
GND
OGc
H2SLc
V1T
V2T
V3T
V4T
RDcd
R2cd
R1d
VDDd
VOUTd
GND
OGd
H2 SLd
H2B c
H2S c
H1B c
H1S c
H2B d
H2S d
H1B d
H1S d
ESD
V1B
V2B
V3B
V4B
RDab
R2ab
R1 a
VDDa
VOUTa
GND
OGa
H2SLa
16 Buffer
16 Dark
1 Dummy
(Last VCCD Phase = V1
à
H1S)
1024
Dark Reference Pixels
There are 16 dark reference rows at the top and 16 dark
rows at the bottom of the image sensor. The 24 dark columns
on the left or right side of the image sensor should be used
as a dark reference.
Under normal circumstances use only the center
22 columns of the 24 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 12 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
16 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non-uniformities.
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
1 11 24 16
1024
1024
16 24 11 1
8
1 Dummy
16
16
24 16
HLOD
V1T
V2T
V3T
V4T
DevID
2048H x 2048V
7.4mm x 7.4mm Pixels
16 24
ESD
V1B
V2B
V3B
V4B
RDab
R2ab
R1b
VDDb
VOUTb
GND
OGb
H2SLb
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
1 11 24 16
8
1024
16 24 11 1
8
HLOD
H2Bb
H2Sb
H1Bb
H1Sb
H2Ba
H2Sa
H1Ba
H1Sa
Figure 2. Block Diagram
Image Acquisition
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3
SUB
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
ESD Protection
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power-Up and Power-Down Sequence section.
KAI−04070
Bayer Color Filter Pattern
SUB
RDcd
R2cd
R1c
VDDc
VOUTc
GND
OGc
H2SLc
RDcd
R2cd
R1d
VDDd
VOUTd
GND
OGd
H2SLd
V1T
V2T
V3T
V4T
DevID
ESD
24 16
H2Bc
H2Sc
H1Bc
H1Sc
H2Bd
H2Sd
H1Bd
H1Sd
V1T
V2T
V3T
V4T
V1B
V2B
V3B
V4B
RDab
R2ab
R1a
VDDa
VOUTa
GND
OGa
H2SLa
TRUESENSE Sparse Color Filter Pattern
SUB
RDcd
R2cd
R1c
VDDc
VOUTc
GND
OGc
H2SLc
RDcd
R2cd
R1d
VDDd
VOUTd
GND
OGd
H2SLd
V1T
V2T
V3T
V4T
DevID
ESD
24 16
H2Bc
H2Sc
H1Bc
H1Sc
H2Bd
H2Sd
H1Bd
H1Sd
V1T
V2T
V3T
V4T
V1B
V2B
V3B
V4B
RDab
R2ab
R1a
VDDa
VOUTa
GND
OGa
H2SLa
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
1 11 24 16
1024
1024
16 24 11 1
8
1Dummy
16
16
B G
G R
B G
G R
HLOD
2048 (H)
×
2048 (V)
7.4
mm
×
7.4
mm
Pixels
16 24
ESD
B G
G R
B G
G R
V1B
V2B
V3B
V4B
RDab
R2ab
R1b
VDDb
VOUTb
GND
OGb
H2SLb
1 11 24 16
8
1 11 24 16
1 11 24 16
8
Figure 4. TRUESENSE Sparse Color Filter Pattern
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
1024
1024
16 24 11 1
8
16 Buffer
16 Dark
1 Dummy
(Last VCCD Phase = V1
→
H1S)
HLOD
H2Bb
H2Sb
H1Bb
H1Sb
Figure 3. Bayer Color Filter Pattern
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
HLOD
1024
1024
16 24 11 1
8
1 Dummy
16
16
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
H2Ba
H2Sa
H1Ba
H1Sa
P
R
P
G
2048 (H)
×
2048 (V)
7.4
mm
×
7.4
mm
Pixels
SUB
16 24
ESD
G
P
B
P
P
G
P
B
R
P
G
P
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
V1B
V2B
V3B
V4B
RDab
R2ab
R1b
VDDb
VOUTb
GND
OGb
H2SLb
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
1024
1024
16 24 11 1
8
16 Buffer
16 Dark
1 Dummy
(Last VCCD Phase = V1
→
H1S)
HLOD
H2Bb
H2Sb
H1Bb
H1Sb
H2Ba
H2Sa
H1Ba
H1Sa
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SUB
KAI−04070
Physical Description
Pin Description and Device Orientation
V3T
V1T
VDDc
GND
Rc
H2SLc H1Bc
H2Sc
R2cd
H2Sd
H1Bd
H2SLd
Rd
GND
VDDd
V1T
V3T
67
65
63
V2T
61
59
57
OGc
55
H2Bc
53
H1Sc
51
SUB
49
H1Sd
47
H2Bd
45
OGd
43
41
39
V2T
37
35
ESD V4T
VOUTc RDcd
RDcd VOUTd
V4T DevID
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
Pixel (1,1)
4
V4B
6
V2B
8
10
12
OGa
14
H2Ba
16
H1Sa
18
SUB
20
H1Sb
22
H2Bb
24
OGb
26
28
30
V2B
32
V4B
34
ESD
VOUTa RDab
RDab VOUTb
1
V3B
3
V1B
5
VDDa
7
GND
9
Ra
11
13
15
H2Sa
17
R2ab
19
H2Sb
21
H1Bb
23
H2SLb
25
Rb
27
GND
29
VDDb
31
V1B
33
V3B
H2SLa H1Ba
Figure 5. Package Pin Designations − Top View
Table 4. PACKAGE PIN DESCRIPTION
Pin
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
V3B
V1B
V4B
VDDa
V2B
GND
VOUTa
Ra
RDab
H2SLa
OGa
H1Ba
H2Ba
H2Sa
H1Sa
R2ab
SUB
H2Sb
H1Sb
H1Bb
Vertical CCD Clock, Phase 3, Bottom
Vertical CCD Clock, Phase 1, Bottom
Vertical CCD Clock, Phase 4, Bottom
Output Amplifier Supply, Quadrant a
Vertical CCD Clock, Phase 2, Bottom
Ground
Video Output, Quadrant a
Reset Gate, Standard (High) Gain, Quadrant a
Reset Drain, Quadrants a & b
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
Output Gate, Quadrant a
Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
Horizontal CCD Clock, Phase 2, Storage, Quadrant a
Horizontal CCD Clock, Phase 1, Storage, Quadrant a
Reset Gate, Low Gain, Quadrants a & b
Substrate
Horizontal CCD Clock, Phase 2, Storage, Quadrant b
Horizontal CCD Clock, Phase 1, Storage, Quadrant b
Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
Description
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