UNISONIC TECHNOLOGIES CO., LTD
4066
QUAD BILATERAL SWITCH
DESCRIPTION
CMOS IC
The UTC
4066
is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals.
FEATURES
* Wide supply voltage range: 3V ~ 15V.
* High noise immunity : 0.45V
DD
(typ.)
* Wide range of digital and ± 7.5V
PEAK
analog switching
* “ON” resistance for 15V operation : 80Ω
* Matched ”ON” resistance :
∆R
ON
=5Ω (typ.)
over 15V signal input
* “ON” resistance flat over peak-to-peak signal range
* High “ON” / “OFF” : 65 dB (typ.)
output voltage ratio @ f
IS
=10kHz, R
L
=10kΩ
* High degree linearity: 0.1% distortion (typ.).
@ f
IS
=1kHz, V
IS
=5Vp-p.
*
V
DD
-V
SS
=10V, R
L
=10kΩ
* Extremely low ”OFF” : 0.1nA (typ.)
* switch leakage @V
DD
-V
SS
=10V, T
A
=25°C
* Extremely high control input impedance : 10
12
Ω
(typ.)
* Low crosstalk : -50dB (typ.)
* between switches @ f
IS
=0.9MHz, R
L
=1kΩ
* Frequency response, switch ”ON” : 40MHz (typ.)
ORDERING INFORMATION
Ordering Number
Lead Free
4066L-D14-T
-
-
Halogen Free
4066G-D14-T
4066G-S14-R
4066G-P14-R
Package
DIP-14
SOP-14
TSSOP-14
Packing
Tube
Tape Reel
Tape Reel
MARKING
DIP-14
14 13
SOP-14 / TSSOP-14
12
11
10
9
8
UTC
Date Code
Lot Code
4066G
5
6
7
1
2
3
4
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Copyright © 2014 Unisonic Technologies Co., Ltd
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QW-R502-009.F
4066
PIN CONFIGURATION
CMOS IC
SCHEMATIC DIAGRAM
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QW-R502-009.F
4066
ABSOLUTE MAXIMUM RATINGS
(V
SS
=0V, unless otherwise specified))
PARAMETER
SYMBOL
V
DD
V
IN
CMOS IC
RATINGS
UNIT
Supply Voltage
-0.5 ~ +18
V
Input Voltage
-0.5 ~ V
CC
+0.5
V
DIP-14
700
Power Dissipation
P
D
mW
SOP-14/TSSOP-14
500
Junction Temperature
T
J
+125
C
Storage Temperature
T
STG
-40 ~ +150
C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
(V
SS
=0V, unless otherwise specified)
PARAMETER
SYMBOL
V
DD
V
IN
T
OPR
RATINGS
3 ~ 15
0 ~ V
DD
-40 ~ +85
UNIT
V
V
C
Supply Voltage
Input Voltage
Operating Temperature Range
DC ELECTRICAL CHARACTERISTICS
(V
SS
=0V, unless otherwise specified)
PARAMETER
SYMBOL
I
DD
V
DD
=5V
V
DD
=10V
V
DD
=15V
V
C
=0
R
L
=10kΩ~ (V
DD
-V
SS
/2)
V
C
=V
DD
, V
SS
~ V
DD
R
L
=10kΩ~ (V
DD
-V
SS
/2)
V
C
=V
DD
, V
IS
=V
SS
~V
DD
V
DD
=5V
V
DD
=10V
V
DD
=15V
V
DD
=10V
V
DD
=15V
CONDITIONS
MIN
TYP MAX UNIT
0.01 1.0
μA
0.01 2.0
0.01 4.0
±0.1
270
120
80
10
5
±50
1050
400
240
nA
Ω
Ω
Quiescent Device Current
SIGNAL INPUTS AND OUTPUTS
Input or Output Leakage Switch
“OFF”
“ON” Resistance
∆”ON”
Resistance Between Any 2 of
4 Switches
CONTROL INPUTS
I
IS
R
ON
∆R
ON
V
DD
=5V
2.25 1.5
V
IS
=V
SS
and V
DD
V
OS
=V
DD
and V
SS
Low Level Input Voltage
V
ILC
V
DD
=10V
4.5
3.0
I
IS
=±10μA
V
DD
=15V
6.75 4.0
3.5 2.75
V
DD
=5V
HIGH Level Input Voltage
V
IHC
V
DD
=10V (Note)
7.0
5.5
V
DD
=15V
11.0 8.25
V
DD
-V
SS
=15V, V
DD
≧
V
IS
≧
V
SS,
±10
-5
±0.3
Input Current
I
IN
V
DD
≧
V
C
≧
V
SS
Note: Conditions for V
IHC
: (a) V
IS
=V
DD
, I
OS
=standard B series I
OH
. (b) V
IS
=0V, I
OL
=standard B series I
OL
V
V
μA
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QW-R502-009.F
4066
(T
A
=25C, t
R
=t
F
=20 ns and V
SS
=0V unless otherwise)
PARAMETER
SYMBOL
Propagation Delay Time Signal
Input to Signal Output
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Frequency Response -Switch
“ON” (Frequency at-3dB)
Feedthrough - Switch “OFF”
(Frequency at –50 dB)
Crosstalk Between Any Two
Switches(Frequency at-50dB)
Crosstalk; Control Input to
Signal Output
Maximum Control Input
Signal Input Capacitance
Signal Output Capacitance
Feedthrough Capacitance
Control lnput Capacitance
T
PHL
, T
PLH
CONDITIONS
V
DD
=5V
V
DD
=10V
V
DD
=15V
V
DD
=5V
V
DD
=10V
V
DD
=15V
R
L
=1.0kΩ, C
L
=50pF
(Fig. 2, 3)
V
DD
=5V
V
DD
=10V
V
DD
=15V
t
PHZ
, t
PLZ
V
C
=V
DD
=5V, V
SS
= -5V
R
L
=10kΩ, V
IS
=5V
P-P
, f=1kHz, (Fig. 4)
V
C
=V
DD
=5V, V
SS
= -5V
R
L
=1kΩ, V
IS
=5Vp-p
20 Log10 V
OS
/V
OS
(1kHz)-dB (Fig. 4)
V
DD
=5.0V, V
CC
=V
SS
= -5.0V, R
L
=1kΩ,
V
IS
=5.0V
P-P
, 20Log
10
, V
OS
/V
IS
= -50dB,
(Fig. 4)
V
DD
=V
C
(A)=5.0V; V
SS
=V
C
(B)=5.0V,
R
L
=1kΩ, V
IS
(A)=5.0V
P-P
, 20Log
10
,
V
OS
(B)/V
IS
(A)= -50dB (Fig. 5)
V
DD
=10V, R
L
=10kΩ, R
IN
=1.0kΩ,
V
CC
=10V Square Wave, C
L
=50pF
(Fig. 6)
V
DD
=5.0V
R
L
=1.0kΩ, C
L
=50pF (Fig. 7)
V
DD
=10V
V
OS
(f) =1/2Vos (1.0kHz)
V
DD
=15V
C
IS
C
OS
V
DD
=10V
C
IOS
V
C
=0V
C
IN
MIN
CMOS IC
AC ELECTRICAL CHARACTERISTICS
(AC Parameters are guaranteed by DC correlated testing)
TYP MAX UNIT
25
55
ns
15
35
10
25
125
60
50
125
60
50
0.1
40
%
MHz
ns
ns
V
C
=V
DD
, C
L
=50Pf (Figure1)
R
L
=200k
R
L
=1.0kΩ, C
L
=50pF
(Fig. 2, 3)
t
PZH
, t
PLZ
1.25
MHz
0.9
MHz
150
6.0
8.0
8.5
8.0
8.0
0.5
5.0
mV
p-p
MHz
pF
pF
pF
pF
7.5
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QW-R502-009.F
4066
SPECIAL CONSIDERATIONS
CMOS IC
In applications where separate power sources are used to drive V
DD
and the signal input, the V
DD
current capability
should exceed V
DD
/R
L
(R
L
=effective external load of the UTC
4066
bilateral switches).This provision avoids any
permanent current flow or clamp action of the V
DD
supply when power is applied or removed from UTC 4066.
In certain applications, the external load-resistor current may include both V
DD
and Signal-line components. To
avoid drawing V
DD
current when switch current flows into terminals 1,4,8 or 11,the voltage drop across the
bidirectional swith must not exceed 0.6V at T
A
≤
25°C, or 0.4V at T
A
>25°C (calculated from R
ON
values shown).
NO V
DD
current will flow through R
L
if the switch current flows into terminals2, 3, 9 or 10.
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
V
C
V
DD
V
DD
CONTROL
1 OF 4
OUT/IN
IN/OUT
SWITCHES
V
SS
V
DD
R
L
1KΩ
V
OS
C
L
50pF
t
PZL
V
DD
50%
0V
V
DD
V
OL
t
PZL
90%
0V
V
DD
V
OL
10%
V
DD
t
PLZ
50%
t
PLZ
V
IS
=0V
Fig. 3 t
PZL
, t
PLZ
Propagation Delay Time Control to Signal Output
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QW-R502-009.F
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