DS2148 datasheet, PDF - EEWORLD Datasheet

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DS2148: Description5V E1/T1/J1 Line Interface; File Size521KB，75 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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DS2148 Overview

5V E1/T1/J1 Line Interface

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DS2148/DS21Q48

5V E1/T1/J1 Line Interface

www.maxim-ic.com

FEATURES

Complete E1, T1, or J1 line interface unit

(LIU)

Supports both long- and short-haul trunks

Internal software-selectable receive-side

termination for 75Ω/100Ω/120W

5V power supply

32-bit or 128-bit crystal-less jitter attenuator

requires only a 2.048MHz master clock for

both E1 and T1 with option to use 1.544MHz

for T1

Generates the appropriate line build outs,

with and without return loss, for E1 and

DSX-1 and CSU line build outs for T1

AMI, HDB3, and B8ZS, encoding/decoding

16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output synthesized to

recovered clock

Programmable monitor mode for receiver

Loopbacks and PRBS pattern generation/

detection with output for received errors

Generates/detects in-band loop codes, 1 to 16

bits including CSU loop codes

8-bit parallel or serial interface with optional

hardware mode

Multiplexed and nonmultiplexed parallel bus

supports Intel or Motorola

Detects/generates blue (AIS) alarms

NRZ/bipolar interface for TX/RX data I/O

Transmit open-circuit detection

Receive Carrier Loss (RCL) indication

(G.775)

High-Z State for TTIP and TRING

50mA (rms) current limiter

PIN DESCRIPTION

44 TQFP

7mm

CABGA

ORDERING INFORMATION

Single-Channel Devices:

DS2148TN 44-Pin TQFP

DS2148T

44-Pin TQFP

DS2148GN 7mm CABGA

DS2148G

7mm CABGA

Four-Channel Devices:

DS21Q48N (Quad) BGA

DS21Q48

(Quad) BGA

(-40°C to +85°C)

C to +70

(-40°C to +85°C)

C to +70

(-40°C to +85°C)

C to +70

1 of 75

REV: 082504

DS2148/Q48

TABLE OF CONTENTS

LIST OF FIGURES............................................................................................................................... 4

LIST OF TABLES ................................................................................................................................ 5

INTRODUCTION................................................................................................................................. 6

3.1 DOCUMENT REVISION HISTORY ............................................................................................ 6

4. PIN DESCRIPTION ............................................................................................................................. 9

5. HARDWARE MODE ......................................................................................................................... 22

5.1 REGISTER MAP .......................................................................................................................... 23

5.2 PARALLEL PORT OPERATION................................................................................................ 24

5.3 SERIAL PORT OPERATION ...................................................................................................... 24

6. CONTROL REGISTERS.................................................................................................................... 28

6.1 DEVICE POWER-UP AND RESET ............................................................................................ 31

7 STATUS REGISTERS ....................................................................................................................... 34

8. DIAGNOSTICS .................................................................................................................................. 39

8.1 IN-BAND LOOP CODE GENERATION AND DETECTION ................................................... 39

8.2 LOOPBACKS ............................................................................................................................... 43

8.2.1 Remote Loopback (RLB)......................................................................................................... 43

8.2.2 Local Loopback (LLB)............................................................................................................ 43

8.2.3 Analog Loopback (LLB) ......................................................................................................... 44

8.2.4 Dual Loopback (DLB) ............................................................................................................ 44

8.3 PRBS GENERATION AND DETECTION ................................................................................. 44

8.4 ERROR COUNTER...................................................................................................................... 44

8.4.1 Error Counter Update ............................................................................................................ 45

8.5 ERROR INSERTION.................................................................................................................... 45

9. ANALOG INTERFACE ..................................................................................................................... 46

9.1 RECEIVER .................................................................................................................................... 46

9.2 TRANSMITTER ........................................................................................................................... 47

9.3 JITTER ATTENUATOR .............................................................................................................. 47

9.4 G.703 SYNCHRONIZATION SIGNAL ...................................................................................... 48

10. DS21Q48 QUAD LIU......................................................................................................................... 56

11. DC CHARACTERISTICS.................................................................................................................. 60

12. AC CHARACTERISTICS.................................................................................................................. 62

13. MECHANICAL DIMENSIONS......................................................................................................... 71

13.1 MECHANICAL DIMENSIONS—QUAD VERSION................................................................. 73

3 of 75

DS2148/Q48

1. LIST OF FIGURES

Figure 3-1 DS2148 BLOCK DIAGRAM..................................................................................................... 7

Figure 3-2 RECEIVE LOGIC ...................................................................................................................... 8

Figure 3-3 TRANSMIT LOGIC ................................................................................................................... 9

Figure 4-1 PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0) ............................................ 21

Figure 4-2 SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) .......................................................... 21

Figure 4-3 HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) ............................................................ 22

Figure 5-1 SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1.................................. 25

Figure 5-2 SERIAL PORT OPERATION FOR READ ACCESS MODE 2 ............................................. 25

Figure 5-3 SERIAL PORT OPERATION FOR READ ACCESS MODE 3 ............................................. 26

Figure 5-4 SERIAL PORT OPERATION FOR READ ACCESS MODE 4 ............................................. 26

Figure 5-5 SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1&2 ...……………27

Figure 5-6 SERIAL PORT OPERATION FOR WRITE ACCESS MODES 3&4 …………...…………27

Figure 9-1 BASIC INTERFACE ………………………………………………………………………..50

Figure 9-2 PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION.................... 51

Figure 9-3 PROTECTED INTERFACE USING EXTERNAL RECEIVE TERMINATION .................. 52

Figure 9-4 E1 TRANSMIT PULSE TEMPLATE...................................................................................... 53

Figure 9-5 T1 TRANSMIT PULSE TEMPLATE...................................................................................... 54

Figure 9-6 JITTER TOLERANCE............................................................................................................. 55

Figure 9-7 JITTER ATTENUATION ........................................................................................................ 55

Figure 10-1 BGA 12 x 12 PIN LAYOUT .................................................................................................. 59

Figure 12-1 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0) ............................................ 63

Figure 12-2 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)........................................... 63

Figure 12-3 MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) ............................................ 64

Figure 12-4 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1) ............................................ 66

Figure 12-5 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)........................................... 66

Figure 12-6 MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................. 67

Figure 12-7 MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1)................................ 67

Figure 12-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)........................................................................ 68

Figure 12-9 RECEIVE SIDE TIMING ...................................................................................................... 69

Figure 12-10 TRANSMIT SIDE TIMING................................................................................................. 70

4 of 75

DS2148/Q48

2. LIST OF TABLES

Table 4-1 BUS INTERFACE SELECTION ................................................................................................ 9

Table 4-2a PIN ASSIGNMENT................................................................................................................. 10

Table 4-2b PIN DESCRIPTIONS (Sorted by Pin Name, DS2148T Pin Numbering) ............................... 11

Table 4-3a PIN ASSIGNMENT IN SERIAL PORT MODE..................................................................... 13

Table 4-3b PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T Pin

Numbering) .......................................................................................................................................... 14

Table 4-4a PIN ASSIGNMENT IN HARDWARE MODE....................................................................... 16

Table 4-4b PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin

Numbering) .......................................................................................................................................... 16

Table 4-5 LOOPBACK CONTROL IN HARDWARE MODE ................................................................ 20

Table 4-6 TRANSMIT DATA CONTROL IN HARDWARE MODE ..................................................... 20

Table 4-7 RECEIVE SENSITIVITY SETTINGS...................................................................................... 20

Table 4-8 MONITOR GAIN SETTINGS .................................................................................................. 20

Table 4-9 INTERNAL RX TERMINATION SELECT............................................................................. 20

Table 4-10 MCLK SELECTION................................................................................................................ 20

Table 5-1 REGISTER MAP ....................................................................................................................... 23

Table 6-1 MCLK SELECTION.................................................................................................................. 29

Table 6-2 RECEIVE SENSITIVITY SETTINGS...................................................................................... 31

Table 6-3 BACK PLANE CLOCK SELECT............................................................................................. 32

Table 6-4 MONITOR GAIN SETTINGS .................................................................................................. 32

Table 6-5 INTERNAL RX TERMINATION SELECT............................................................................. 33

Table 7-1 RECEIVED ALARM CRITERIA ............................................................................................. 35

Table 7-2 RECEIVE LEVEL INDICATION............................................................................................. 38

Table 8-1 TRANSMIT CODE LENGTH................................................................................................... 40

Table 8-2 RECEIVE CODE LENGTH ...................................................................................................... 40

Table 8-3 DEFINITION OF RECEIVED ERRORS.................................................................................. 44

Table 8-4 FUNCTION OF ECRS BITS AND RNEG PIN ........................................................................ 45

Table 9-1 LINE BUILD OUT SELECT FOR E1 IN REGISTER CCR4 (ETS = 0) ................................. 48

Table 9-2 LINE BUILD OUT SELECT FOR T1 IN REGISTER CCR4 (ETS = 1) ................................. 48

Table 9-3 TRANSFORMER SPECIFICATIONS FOR 5V OPERATION ............................................... 49

Table 10-1 DS21Q48 PIN ASSIGNMENT................................................................................................ 56

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DS2148 Related Products

	DS2148	DS2148G	DS2148GN	DS2148T	DS2148TN	DS21Q48	DS21Q48N
Description	5V E1/T1/J1 Line Interface	DATACOM, PCM TRANSCEIVER, BGA49	DATACOM, PCM TRANSCEIVER, BGA49	DATACOM, PCM TRANSCEIVER, PQFP44	DATACOM, PCM TRANSCEIVER, PQFP44	DATACOM, PCM TRANSCEIVER, PBGA144	DATACOM, PCM TRANSCEIVER, PBGA144
Is it Rohs certified?	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	-	DALLAS	DALLAS	DALLAS	DALLAS	DALLAS	DALLAS
package instruction	-	CABGA-49	CABGA-49	TQFP-44	TQFP-44	BGA-144	BGA-144
Reach Compliance Code	-	unknow	unknow	unknow	unknow	unknow	unknow
JESD-30 code	-	S-XBGA-B49	S-XBGA-B49	S-PQFP-G44	S-PQFP-G44	S-PBGA-B144	S-PBGA-B144
JESD-609 code	-	e0	e0	e0	e0	e0	e0
Number of functions	-	1	1	1	1	1	1
Number of terminals	-	49	49	44	44	144	144
Maximum operating temperature	-	70 °C	85 °C	70 °C	85 °C	70 °C	85 °C
Package body material	-	UNSPECIFIED	UNSPECIFIED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	FBGA	FBGA	QFP	QFP	BGA	BGA
Encapsulate equivalent code	-	BGA49,7X7,32	BGA49,7X7,32	TQFP44,.47SQ,32	TQFP44,.47SQ,32	BGA144,12X12,50	BGA144,12X12,50
Package shape	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	GRID ARRAY	GRID ARRAY	FLATPACK	FLATPACK	GRID ARRAY	GRID ARRAY
power supply	-	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum slew rate	-	0.125 mA	0.125 mA	0.125 mA	0.125 mA	0.125 mA	0.125 mA
Nominal supply voltage	-	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	-	YES	YES	YES	YES	YES	YES
technology	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Telecom integrated circuit types	-	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER
Temperature level	-	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	BALL	BALL	GULL WING	GULL WING	BALL	BALL
Terminal pitch	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm	1.27 mm	1.27 mm
Terminal location	-	BOTTOM	BOTTOM	QUAD	QUAD	BOTTOM	BOTTOM

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