EN27LN4G08
EN27LN4G08
4 Gigabit (512M x 8), 3.3 V NAND Flash Memory
Features
•
Voltage Supply: 2.7V ~ 3.6V
•
Organization
- Memory Cell Array :
(512M + 16M) x 8bit
- Data Register : (2K + 64) x 8bit
•
Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
•
Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 25ns (Min.)
•
Memory Cell: 1bit/Memory Cell
•
Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
•
Reliable CMOS Floating-Gate Technology
- ECC Requirement: 4 bit/512 Byte
- Endurance: 100K Program/Erase Cycles
- Data Retention: 10 Years
•
Command Register Operation
•
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
•
NOP: 4 cycles
•
Cache Program Operation for High Performance
Program
•
Cache Read Operation
•
Copy-Back Operation
- EDO mode
- OTP Operation
- Two-Plane Operation
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03
EN27LN4G08
General Description
The device is a 512Mx8bit with spare 16Mx8bit capacity. The device is offered in 3.3V VCC Power
Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid
data while old data is erased.
The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32
series connected Flash cells. A program operation allows to write the 2112-Word page in typical 250us
and an erase operation can be performed in typical 2ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per Word. The I/O pins serve as the ports for
address and command inputs as well as data input/output. The copy back function allows the
optimization of defective blocks management: when a page program operation fails the data can be
directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. The cache program feature allows the data insertion in the cache register while
the data register is copied into the Flash array. This pipelined program operation improves the program
throughput when long files are written inside the memory. A cache read feature is also implemented.
This feature allows to dramatically improving the read throughput when consecutive pages have to be
streamed out. This device includes extra feature: Automatic Read at Power Up.
Pin Configuration
(TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)
NC
NC
NC
NC
NC
NC
RY/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
Standard
TSOP
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03
EN27LN4G08
Table 1. Pin Description
Symbol
I/O0 – I/O7
Function
The I/O pins are used to input command, address and data, and
Data Inputs/Outputs to output data during read operations. The I/O pins float to Hi-Z
when the chip is deselected or when the outputs are disabled.
The CLE input controls the activating path for commands sent to
Command Latch
the command register. Commands are latched into the command
Enable
register through the I/O ports on the rising edge of the WE# signal
with CLE high.
The ALE input controls the activating path for address sent to the
internal address registers. Addresses are latched into the address
Address Latch
register through the I/O ports on the rising edge of WE# with ALE
Enable
high.
The CE# input is the device selection control. When the device is
in the Busy state, CE# high is ignored, and the device does not
Chip Enable
return to standby mode in program or erase operation. Regarding
CE# control during read operation, refer to ’Page read’ section of
Device operation.
The RE# input is the serial data-out control, and when it is low, it
active drives the data onto the I/O bus. Data is valid t
REA
after the
Read Enable
falling edge of RE# which also increments the internal column
address counter by one.
The WE# input controls writes to the I/O port. Commands,
Write Control
address and data are latched on the rising edge of the WE# pulse.
The WP# pin provides inadvertent program/erase protection
Write Protect
during power transitions. The internal high voltage generator is
reset when the WP# pin is active low.
The R/B# output indicates the status of the device operation.
When low, it indicates that a program, erase or random read
Ready/Busy Output
operation is in process and returns to high state upon completion.
It is an open drain output and does not float to Hi-Z condition
when the chip is deselected or when outputs are disabled.
Power Supply
Ground
No Connection
Lead is not internally connected.
V
CC
is the power supply for device.
Pin Name
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
V
CC
V
SS
NC
Note:
Connect all V
CC
and V
SS
pins of each device to common power supply outputs. Do not leave V
CC
or V
SS
disconnected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03
EN27LN4G08
Block Diagram
Functional Block Diagram
Array Organization
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03
EN27LN4G08
Address Cycle Map
I/O 0
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
Note:
A0
A8
A12
A20
A28
I/O 1
A1
A9
A13
A21
A29
I/O 2
A2
A10
A14
A22
L*
I/O 3
A3
A11
A15
A23
L*
I/O 4
A4
L*
A16
A24
L*
I/O 5
A5
L*
A17
A25
L*
I/O 6
A6
L*
A18
A26
L*
I/O 7
A7
L*
A19
A27
L*
Address
Column Address
Column Address
Row Address
Row Address
Row Address
1. Column Address : Starting Address of the Register.
2. * L must be set to “Low”.
3. * The device ignores any additional input of address cycles than required.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03
Microcontroller MCU
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