EN71SN10E
EN71SN10E
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
•
Multi-Chip Package
- NAND Flash Density: 1-Gbits
- Mobile DDR SDRAM Density: 256-Mbit
•
Device Packaging
- 107 balls FBGA
Area: 10.5x13 mm; Height: 1.2 mm
NAND FLASH
•
Voltage Supply: 1.7V ~ 1.95V
•
Organization
- Memory Cell Array :
(128M + 4M) x 8bit for 1Gb
- Multiplexed address/ data
- Data Register : (2K + 64) x 8bit
•
Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
•
Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
•
Memory Cell: 1bit/Memory Cell
•
Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
Reliable CMOS Floating-Gate Technology
Endurance:
- 100K Program/Erase Cycles (with 1 bit/528
bytes ECC)
- Data Retention: 10 Years
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program/Read Operation
Copy-Back Operation
EDO mode
OTP Operation
1
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Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
•
Operating Temperature :-30 °C to +85 °C
Mobile DDR SDRAM
•
•
•
•
Density: 256M bits
Organization: 4M words x16 bits x 4 banks
Power supply: V
DD
/V
DDQ
= 1.70~1.95V
Speed: 400Mbps (max.) for data rate
•
Internal pipelined double-data-rate architecture,
two data access per clock cycle
•
Bi-directional data strobe (DQS)
•
No DLL; CLK to DQS is not synchronized.
•
Differential clock inputs (CLK and CLK# )
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Four bank operation
CAS Latency: 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated
Self Refresh)
- DS (Drive Strength)
•
All inputs except data & DM are sampled at the
rising edge of the system clock(CLK)
•
DQS is edge-aligned with data for READ;
center-aligned with data for WRITE
•
Data mask (DM) for write masking only
•
Auto & Self refresh
•
7.8us refresh interval (64ms refresh period, 8K
cycle)
•
LVCMOS-compatible inputs
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This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07
EN71SN10E
Ordering Information
NAND Flash
Product ID
Configuration
EN71SN10E-45CFWP
1Gb
(128M X 8 bits)
Speed
45ns
Configuration
Speed
Mobile DDR SDRAM
Package
256Mb (4 Banks
200MHz 107 ball FBGA
X 4M X 16 bits)
Operation
Temperature
Range
Wireless
MCP Block Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07
EN71SN10E
Ball Configuration
(TOP VIEW)
(FBGA 107, 10.5mmx13mmx1.2mm Boby, 0.8mm Ball Pitch)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07
EN71SN10E
Table 1. Ball Description
Pin Name
NAND
VCC
VSS
I/O0-7
ALE
CLE
CE#
RE#
WE#
WP#
R / B#
Supply
Supply
Input/output
Input
Input
Input
Input
Input
Input
Output
Supply Voltage
Ground
Data input/outputs, address inputs, or command inputs
Address Latch Enable
Command Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready/Busy (open-drain output)
Power Supply
Ground
DQ’s Power Supply: Isolated on the die for improved noise immunity.
Ground
CLK and CLK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CLK and negative edge of CLK# .
Input and output data is referenced to the crossing of CLK and CLK# (both
directions of crossing). Internal clock signals are derived from CLK, CLK#
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for SELF
REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CLK,
CLK# and CKE, are disabled during power-down and self refresh mode which are
contrived for low standby power consumption.
CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is considered part of
the command code.
CAS#, RAS# , and WE
D
# (along with CS# ) define the command being entered.
Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of
the memory array in the respective bank. The address inputs also provide the
opcode during a MODE REGISTER SET command.
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Output with read data, input with write data. Edge-aligned with read data, centered
with write data. Used to capture write data. LDQS corresponds to the data on DQ0-
DQ7, UDQS corresponds to the data on DQ8-DQ15.
DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading matches the DQ
and DQS loading. LDM corresponds to the data on DQ0-DQ7, UDM corresponds to
the data on DQ8-DQ15.
4
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Type
Function
Mobile DDR SDRAM
VDD
Supply
VSSD
Supply
VDDQ
Supply
VSSQ
Supply
CLK, CLK#
Input
CKE
Input
CS#
RAS# ,
CAS# , WE
D
#
A0-A12
Input
Input
Input
BA0, BA1
DQ0-15
LDQS, UDQS
Input
Input /
Output
Input /
Output
LDM, UDM
Input
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2012/12/07
EN71SN10E
PACKAGE DIMENSION
107-BALL FBGA ( 10.5x13 mm )
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07
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