EN71SN2BGD11
EN71SN2BGD11
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
•
Multi-Chip Package
- NAND Flash Density: 2-Gbits
- Mobile DDR SDRAM Density: 1-Gbits
•
Device Packaging
- 137 balls BGA
Area: 10.5x13 mm; Height: 1.2 mm
- 130 balls BGA
Area: 8x9 mm; Height: 1.0 mm
NAND FLASH
•
Voltage Supply: 1.7V ~ 1.95V
•
Organization
- Memory Cell Array :
(256M + 8M) x 8bit for 2Gb
- Multiplexed address/ data
- Data Register : (2K + 64) x 8bit
•
Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
•
Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
•
Memory Cell: 1bit/Memory Cell
•
Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
•
Reliable CMOS Floating-Gate Technology
- ECC Requirement: 4 bit/512 bytes
- Endurance: 100K Program/Erase Cycles
- Data Retention: 10 Years
•
Command Register Operation
•
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
•
NOP: 4 cycles
•
Cache Program/Read Operation
•
Copy-Back Operation
•
Two-plane Operation
•
EDO mode
•
Bad-Block-Protect
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
•
Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
•
Operating Temperature :-25 °C to +85 °C
Mobile DDR SDRAM
•
•
•
•
•
•
•
•
Density: 1G bits
Organization: 8M words x 32 bits x 4 banks
Power supply: V
DD
/V
DDQ
= 1.70~1.95V
Four internal banks for concurrent operation
1.8V LVCMOS-compatible inputs
Programmable Burst Lengths : 2, 4, 8 or 16
Burst Type : Sequential and Interleave
Auto Refresh and Self Refresh Modes
•
Configurable Drive Strength (DS)
•
Optional Partial Array Self Refresh (PASR)
•
On-chip temperature sensor to control self
refresh rate Temperature Compensated Self
Refresh (TCSR)
•
Deep Power Down Mode (DPD)
•
Double-data rate architecture; two data transfer
per clock cycle
•
Bidirectional, data strobe (DQS) is
transmitted/received with data, to be used in
capturing data at the receiver
•
DQS edge-aligned with data for READ; center-
aligned with data for WRITE
•
Differential clock inputs (CLK and CLK# )
•
•
•
•
•
•
•
Commands entered on each positive CLK edge
Data mask (DM) for write data – one mask per byte
Bidirectional data strobe per byte of data (DQS)
Clock Stop capability
Concurrent Auto Precharge option is supported
Status Read Register (SRR)
64ms refresh
1
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/11/29
EN71SN2BGD11
Table 1. Ball Description
Pin Name
Type
Function
Supply Voltage
Ground
The I/O pins are used to input command, address and data, and to output data during read
operations. The I/O pins float to high-z when the chip is deselected or when the outputs are
disabled.
The ALE input controls the activating path for addresses sent to the internal address registers.
Addresses are latched into the address register through the I/O ports on the rising edge of
WE# with ALE high.
The CLE input controls the activating path for commands sent to the internal command
registers. Commands are latched into the command register through the I/O ports on the rising
edge of the WE# signal with CLE high.
The CE# input is the device selection control. When the device is in the Busy state, CE# high
is ignored, and the device does not return to standby mode in program or erase operation.
Regarding CE# control during read operation, refer to ’Page read’ section of Device operation.
The RE# input is the serial data-out control, and when it is active low, it drives the data onto
the I/O bus. Data is valid t
REA
after the falling edge of RE# which also increments the internal
column address counter by one.
The WE# input controls writes to the I/O ports. Commands, address and data are latched on
the rising edge of the WE# pulse.
The WP# pin provides inadvertent write/erase protection during power transitions. The internal
high voltage generator is reset when the WP# pin is active low.
The R/B# output indicates the status of the device operation. When low, it indicates that a
program, erase or random read operation is in progress and returns to high state upon
completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or when outputs are disabled.
NAND Flash
VCC
Supply
VSS
Supply
I/O0-I/O7
ALE
Input/output
Input
CLE
Input
CE#
RE#
WE#
WP#
R / B#
Input
Input
Input
Input
Output
Mobile DDR SDRAM
VDD
Supply
VSSD
Supply
VDDQ
Supply
VSSQ
Supply
CLK, CLK#
Input
CKE
Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
A0-A12
Input
BA0, BA1
Input
Input /
DQ0- DQ31
Output
Input /
DQS0-DQS3
Output
DM0-DM3
Input
NC / DNU
-
Power Supply
Ground
DQ’s Power Supply: Isolated on the die for improved noise immunity.
Ground
CLK and CLK# are differential system clock inputs.
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Input
Bank Address Input
Data Input/Output pins
Data Strobe
Input Data Mask
No Connection / Do Not Use
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/11/29
Embedded System
京公网安备 11010802033920号
EEWORLD
