a
FEATURES
Operation to 48 V Input Voltage
Ultrahigh Efficiency (Up to 95%)
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Wide Current Range
Logic Controlled Micropower Shutdown
Short Circuit Protection
Very Low Dropout Operation
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
APPLICATIONS
Notebook and Palmtop Computers
Portable Instruments
Battery Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies
High Efficiency, Synchronous
Step-Down Switching Regulators
ADP1149/1149-3.3/1149-5
PIN CONFIGURATIONS
16-Lead Plastic DIP
16-Lead Plastic SO
PGATE
V
IN
V
CC
PDRIVE
V
CC
C
T
I
TH
SENSE–
16
CAP
SD2
REG GND
NGATE
PWR GND
SIG GND
VFB (SD1)*
SENSE+
1
2
3
4
5
6
ADP1149
ADP1149-
3.3
ADP1149-
5
15
14
13
12
11
TOP VIEW
7 (Not to Scale) 10
9
8
*FIXED OUTPUT VERSIONS = SD1
GENERAL DESCRIPTION
The ADP1149 is a family of synchronous step-down switching
regulator controllers featuring automatic-sleep mode to maintain
high efficiencies at low output currents. These devices drive
external complementary power MOSFETs at switching fre-
quencies up to 250 kHz using a constant off-time current-mode
architecture.
Special onboard regulation and level-shift circuitry allow opera-
tion at input voltages from dropout to 48 V (60 V absolute
maximum). The constant off-time architecture maintains con-
stant ripple current in the inductor, easing the design of wide
RY
A
IN L
IM ICA
EL N
PR CH
TE DATA
V
IN
1N4148
V
IN
CAP
P-GATE
0.047µF
P-DRIVE
V
CC
V
CC
L*
62µH
input range converters. Current-mode operation provides
excellent line and load transient response. The operating cur-
rent level is user programmable via an external current sense
resistor.
The ADP1149 incorporates automatic power saving sleep
mode operation when load currents drop below the level
required for continuous operation. In sleep mode, standby
power is reduced to only about 8 mW at V
IN
= 12 V. In shut-
down, both MOSFETs are turned off.
C
IN
P-CHANNEL
IRFR9024
100µF
100V
0.068µF
3.3µF
R
SENSE**
0.05Ω
V
OUT
5V/ 2A
ADP1149-5
0V = NORMAL
>2V = SHUTDOWN
3300pF
C
T
470pF
SHUTDOWN 1
SHUTDOWN 2
I
TH
C
T
S-GND
SENSE–
N-DRIVE
P,R-GNDS
SENSE+
D1
1N5819
1000pF
N-CHANNEL
IRFR024
*COILTRONICS CTX62-2-MP
**KRL SL-1-C1-0R050J
C
OUT
220µF
1kΩ
Figure 1. Typical Application
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212 or visit our World Wide Web site at http://www.analog.com.
REV. 0
1
ADP1149/1149-3.3/1149-5–SPECIFICATIONS
Parameter
FEEDBACK VOLTAGE
ADP1149 Only*
FEEDBACK CURRENT
ADP1149 Only*
REGULATED OUTPUT VOLTAGE
ADP1149-3.3*
ADP1149-5*
OUTPUT VOLTAGE LINE
REGULATION
OUTPUT VOLTAGE LOAD
REGULATION
ADP1149-3.3*
ADP1149-5.0*
SLEEP MODE OUTPUT RIPPLE*
INPUT DC SUPPLY CURRENT*
Normal Mode
Sleep Mode
Shutdown
INTERNAL REGULATOR VOLTAGE*
(Sets MOSFET Gate Drive Levels)
V
CC
DROPOUT VOLTAGE
V
CC
3
(@ T
A
= +25 C, V
IN
= 12 V, V
10
= 0 V,
1
unless otherwise noted)
Min
1.21
Typ
1.25
0.2
Max
1.29
1.0
3.43
5.2
+40
Units
V
µA
V
V
mV
Symbol
V
10
I
10
V
OUT
Conditions
2
V
IN
= 9 V
V
IN
= 9 V
I
LOAD
= 700 mA
I
LOAD
= 700 mA
V
IN
= 9 V to 48 V,
I
LOAD
= 700 mA
3.23
4.9
–40
3.33
5.05
dV
OUT
dV
OUT
5 mA < I
LOAD
< 2 A
5 mA < I
LOAD
< 2 A
dV
OUT
I
Q
V
IN
= 12 V
V
IN
= 48 V
V
IN
= 12 V
V
IN
= 48 V
V
IN
= 12 V, V
15
= 2 V
V
IN
= 48 V, V
15
= 2 V
V
IN
= 12 V to 48 V
I
S
= 20 mA
V
IN
= 12 V*
V
IN
= 48 V*
I
LOAD
= 0 A
40
60
50
2
2.2
0.6
0.8
135
300
9.75
10.25
200
–0.2
–0.2
0
0
65
100
mV
mV
mV p-p
P GATE TO SOURCE VOLTAGE (OFF)
CURRENT SENSE THRESHOLD
VOLTAGE
ADP1149 Only
ADP1149-3.3
ADP1149-5.0
NOTES
*Denotes specifications that apply over the full operating temperature range.
1
Pin 10 is a shutdown pin on the ADP1149-3.3 and ADP1149-5 fixed output voltage versions and must be at ground potential for testing.
2
T
J
is calculated from the ambient temperature T
A
and power dissipation P
D
according to the following formulas:
ADP1149AR, ADP1149AR-3, ADP1149AR-5: T
J
= T
A
+ (P
D
×
110°C/W)
ADP1149AN, ADP1149AN-3, ADP1149AN-5: T
J
= T
A
+ (P
D
×
70°C/W)
3
Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.
Specifications subject to change without notice.
RY
A
IN L
IM ICA
EL N
PR CH
TE DATA
V
2
–V
3
V
IN
= 5 V, I
3
= 10 mA
V
IN
–V
1
V
9
–V
8
2.8
3.0
0.9
1.1
170
390
11
250
mA
mA
mA
mA
µA
µA
V
mV
V
V
V
8
= 5 V, V
10
= 1.32 V (Forced)
V
8
= 5 V, V
10
= 1.1 V* (Forced)
V
8
= 3.5 V (Forced)
V
8
= 2.9 V (Forced)*
V
8
= 5.3 V (Forced)
V
8
= 4.4 V (Forced)*
130
130
130
25
150
25
150
25
150
170
170
170
mV
mV
mV
mV
mV
mV
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Model
Output Voltage
Package
Description*
Input Supply Voltage (Pin 2) . . . . . . . . . . . . . . –15 V to +60 V
V
CC
Output Current (Pin 3) . . . . . . . . . . . . . . . . . . . . . 50 mA
V
CC
Input Voltage (Pin 5) . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Continuous Output Current (Pins 4, 13) . . . . . . . . . . . . 50 mA
Sense Voltages (Pins 10, 15) . . . . . . . . . . . . . . . . –0.3 V to V
CC
Shutdown Voltages (Pins 10, 15) . . . . . . . . . . . . . . . . . . . . . 7 V
Operating Temperature Range . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
ADP1149AN
ADP1149AR
ADP1149AN-3.3
ADP1149AR-3.3
ADP1149AN-5
ADP1149AR-5
ADJ
ADJ
3.3 V
3.3 V
5V
5V
PDIP
SO-16
PDIP
SO-16
PDIP
SO-16
*For outline information see Package Information section.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2
REV. 0
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
